System Performance Counters; Table 29: Zbbus Count Register; Table 30: Zbbus Count Compare Registers; Table 31: System Performance Counter Configuration Registers - Broadcom BCM1250 User Manual

User Manual
10/21/02
Note 00_1003_0008 - 00_1003_FFFF is safe for user space access
Bits Name
63:0 count
Bits Name
63:0 compare
S P
YSTEM ERFORMANCE
There are four system performance counters. They count system events and interrupt when saturated. All four
counters are cleared and/or enabled simultaneously. When one counter saturates, all counters are frozen.
Thus, the readings across the four counters cover the same interval. The counters are writable; if they are
written while active the count will continue from the new value (note that the time from the CPU issuing a store
to the counter getting the new value is UNPREDICTABLE).
The counters are all controlled by the perf_cnt_cfg register. This is used to configure the count source for each
counter, to enable or disable all the counters and to clear all the counters. The counter clear bit is write only,
the counters will all be cleared to zero at the end of the cycle that this bit is written with a 1. If both the enable
and clear bits are written with 1 in the same write, the counters are cleared and will start counting the cycle
after the write completes.
If any counter reaches its maximum count the counters will all be disabled (the enable bit in the perf_cnt_cfg
register is cleared) and the perf_cnt_int interrupt will be raised. The interrupt is removed and all the counters
are cleared when the clear bit in the perf_cnt_cfg register is written with a 1.
Since it takes a cycle to disable the counters there is one additional cycle sampled after one (or more) of the
counts reaches FF_FFFF_FFFF during which the counter may overflow (if its source is still active). There is
an additional bit in the performance counters that gets set when they overflow, thus the counter (or counters)
that disabled monitoring could have the value FF_FFFF_FFFF or 100_0000_0000 when the interrupt is seen.
Bits Name
7:0 Counter 0 source
15:8 Counter 1 source
23:16 Counter 2 source
Document 1250_1125-UM100CB-R

Table 29: ZBbus Count Register

zbbus_cycle_count - 00_1003_0000
Default
64'h0 Count of ZBbus cycles since reset. Writes will be ignored.

Table 30: ZBbus Count Compare Registers

zbbus_cycle_cp0 - 00_1002_0C00
zbbus_cycle_cp1 - 00_1002_0C08
Default
64'hFFFF_FFFF Value is compared to zbbus_cycle_count and the interrupt corresponding to
_FFFF_FFFF the register is raised when the count is equal to the value. The interrupt is
cleared by any write to the compare register.
C
OUNTERS

Table 31: System Performance Counter Configuration Registers

perf_cnt_cfg - 00_1002_04C0
Default
8'b0 Sets the source for counter 0.
8'b0 Sets the source for counter 1.
8'b0 Sets the source for counter 2.
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
READ ONLY
Description
Description
Description
Section 4: System Control and Debug Unit Page 61