Management Interface To Phy - Broadcom BCM1250 User Manual

BCM1250/BCM1125/BCM1125H
M I
ANAGEMENT
There is a simple serial management interface between the MAC and the PHY device (or devices). It supports
up to 32 PHY chips (although some PHY devices attach special meaning to address 0) each of which have 32
16-bit registers.
The CPU runs the serial protocol through reading and writing the mac_mdio register.
The management data clock (MDC) is generated by the interface and is an input to the PHY. Data written to
the mdc bit in the mac_mdio register is put out on the MDC pin.
The management data i/o line (MDIO) can be driven by either the MAC or the PHY. It should have an external
1.5K pull-up resistor to pull the line to a 1 when neither is driving. The state of the pin can always be read on
the mdio_in bit in the mac_mdio register. The interface can drive the line by clearing the mdio_dir bit and
writing the data to output to the mdio_out bit.
The MDIO data is latched by the PHY on the rising edge of MDC, so the mdio_dir and mdio_out bits should
never be changed when the mdc bit is changed from a zero to a one. To send data to the PHY the mdio_dir
bit should be cleared, a single write to the mac_mdio register can be used to set mdc low and put the data on
mdio_out. The same data should be written to mdio_out when mdc is set high.
There is a general purpose output pin (GENO) associated with each MAC that is also controlled through the
mac_mdio register. This pin is not part of the standard G/MII connection.
Each MAC interface has its own set of MDIO/MDC/GENO pins. This allows the MAC drivers to be completely
independent with no shared resources, which works well in designs where the MACs are partitioned across
the processors with each running its own operating system. In a system running a single operating system (or
where all the MACs are controlled from a single driver) the PHY addressing scheme can be used to attach the
PHYs for all three MACs to the MDIO/MDC lines of a single MAC. In this case the other MDC lines become
available as general outputs, and the other MDIO lines as GPIOs.
Page 286 Section 9: Ethernet MACs
PHY
NTERFACE TO
B r oadco m C orp or ati on
User Manual
10/21/02
Document 1250_1125-UM100CB-R