Using The L2 Cache As Memory; Figure 12: Level 2 Cache Way Disable Access Address - Broadcom BCM1250 User Manual

User Manual
10/21/02
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Some applications require more control over the on-chip memory than is provided by a cache, and would work
best with a local RAM. A fast RAM can be provided by removing ways from the L2 cache. Each way that is
removed from the cache provides a 128 KByte memory that can be accessed at the same speed as the L2 (or
64KB memory on a 256KB cache).
Ways are removed from cache use (they are removed from the random replacement algorithm) by clearing the
bit corresponding to the way number in the l2_wayen[3:0] register. This is a control register hidden in the L2
cache that can be updated by doing a write to the l2_way_enable space as shown in
any write is made to this address range the data is ignored, and bits [11:8] of the address get written to bits
[3:0] of the register that enables the way. This register resets to have all bits set, so all ways of the cache are
enabled. To remove way 2 from the cache and enable all the other ways the access address would be to the
l2_way_enable space with address bit 10 clear and the others set, giving an address of 00_1004_1B00.
Software should not clear all four bits in the l2_wayen register, the resulting behavior of the cache is
UNPREDICTABLE if there is any L2 cacheable activity in the system (the system will not hang, but data
corruption will occur in one way of the cache). On parts with system revision indicating PERIPH_REV3 and
later the register can be read back from the l2_misc_value register.
39 36
0
The memory removed from the cache must always be accessed as cacheable space. Cacheable transfers are
always done as full blocks and the L2 cache always operates on full cache lines. Writes smaller than a cache
line (which will be the case for most uncacheable stores) will result in the whole line being written with
UNPREDICTABLE data. The ECC logic remains active for the memory. On writes the correct ECC is
generated and written. On reads the ECC is checked, correctable errors are fixed and uncorrectable errors are
flagged as data errors.
Removing ways from the L2 cache reduces both its size and associativity. This is likely to impact the
performance of the processors. A system design trade-off must be made between the control given by having
the local fast memory, and the degradation of cache performance. In general purpose systems using all the
memory as cache is most likely to be the best solution, in well-characterized embedded applications removal
of one way of the L2 cache can improve the predictability of critical loops.
There are two main methods for using ways removed from the L2 cache. The simplest is just to use the
memory as a block of on-chip RAM with a fast access time (that initially contains random data). The second
method is to load data from main memory into the L2 cache and then lock it in place by preventing it being
replaced.
Document 1250_1125-UM100CB-R
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ACHE AS EMORY
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Figure 12: Level 2 Cache Way Disable Access Address

B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
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0 4 1
Written to l2_wayen[3:0]
Figure 12. Whenever
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Section 5: L2 Cache
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