Broadcom BCM1250 User Manual page 265

User Manual
10/21/02
Offset
31 24 23
08 Class Code
R/O 060000
0C BIST Hdr type
R/O 00 R/O 00
10
14 BAR 1 - Reserved R/O 00000000
18
1C
20
Dev: R/O 0000_0008 (Reserved)
24
Dev: R/O 0000_0008 (Reserved)
28
2C SubSystem Id
R/O 0000
30
34 Reserved R/O 000000
38
3C max_lat min_gnt
R/O 00 R/O 00
40 FControl (See
Table 133 on page
R/W 0003
Document 1250_1125-UM100CB-R
Table 127: PCI Interface Configuration Header (Type 0)
Register Bits
16 15 8 7
LatTimer
(Table 130 o (Table 131 on page
n page 241)
R/W 00
BAR 0 - Map Table
Host: R/O 6000_0008
Dev: R/W xx00_0008
BAR 2 - mbox 0
Host: R/O 7000_0008
Dev: R/W xxxx_x008
BAR 3 - mbox 1
Host: R/O 7100_0008
Dev: R/W xxxx_x008
BAR 4 - low memory
Host:R/O 0000_0008
BAR 5 - High Memory
Host:R/O 8000_0008
Cardbus CIS
R/O 00000000
SubSys Vendor
R/O FFFF
ROM Base Address
Host: R/W 73000000
Dev: R/W xxxx0000
Reserved R/O 00000000
Int Pin
R/O 01
Timeout (See
242) Table 132 on page
B r oadco m C orp or ati on
BCM1250/BCM1125/BCM1125H
0
Rev Id Class is a host bridge, revision reflects the
R/O xx interface revision code. The revision code is:
1 - for early prototype BCM1250s.
2 - for initial production BCM1250s
3 - for intial production BCM1125/H and later
BCM1250s
ClineSz The bridge uses a Type 0 device header.
241) R/W 00
Hits to this 16 MB BAR will be translated through
the mapping table. Bit 3 is set to indicate a
prefetchable region.
This BAR is reserved and will always be read as
zero
Hits to this 4 KB BAR are translated into
accesses to the mailbox set and value register
for CPU0.
Hits to this 4 KB BAR are translated into
accesses to the mailbox set and value register
for CPU1.
Hits to this BAR are passed through as
accesses to the low 512MB of memory.
Hits to this BAR are passed through as
accesses to the upper 2GB of the low 4GB of
the address space.
This register is not used.
These registers are not used internally since
this is a host bridge.
If the Configuration registers are read by an
external PCI master with the bridge in Device
Mode the value read from this register will be the
value written from the ZBbus to the SubSysSet
register (offset 8C).
Hits to this 64 KB BAR are translated to
accesses to the boot rom area of memory.
Cap Ptr R/O 00 This register is not used.
This register is not used.
Int Line The Max Latency and Min Grant registers are
R/W 00 used to specify the device preferences for the
latency timer, they default to indicate no special
requirement.
The IntPin register indicates that this device
uses INTA to interrupt in Device Mode.
The IntLine register is used by firmware and
system software.
This additional register allows configuration of
241) R/W 8080 the retry and TRDY timeouts and enable bits for
special features.
Section 8: PCI Bus and HyperTransport Fabric Page
(Cont.)
Description
237