Broadcom BCM1250 User Manual page 22

BCM1250/BCM1125/BCM1125H User Manual
10/21/02
Table 103: Unaligned Buffer Format DMA Descriptor Second Doubleword ..................................................170
Table 104: Status Flags for Ethernet Receive Channel .................................................................................171
Table 105: Option Flags for Ethernet Receive Channel ................................................................................172
Table 106: Status Flags for Ethernet Transmit Channel ................................................................................172
Table 107: Option Flags for Ethernet Transmit Channel ...............................................................................173
Table 108: Status Flags for Synchronous Serial Receive Channel ...............................................................174
Table 109: Option Flags for Synchronous Serial Receive Channel ...............................................................174
Table 110: Status Flags for Synchronous Serial Transmit Channel ..............................................................174
Table 111: Option Flags for Synchronous Serial Transmit Channel ..............................................................174
Table 112: Result in memory of appending the result CRC[31:0]..................................................................179
Table 113: Example CRC configurations .......................................................................................................180
Table 114: Data Mover Descriptor Base Address Register ...........................................................................184
Table 115: Debug Data Mover Descriptor Base Address Register................................................................184
Table 116: Data Mover Descriptor Count Register ........................................................................................185
Table 117: Data Mover Current Descriptor Address ......................................................................................185
Table 118: Data Mover CRC Definition Registers (Only if System Revision >= PERIPH_REV3) .................185
Table 119: Data Mover CRC/Checksum Definition Registers (Only if System Revision >= PERIPH_REV3)186
Table 120: Data Mover Channel Partial Result Registers (Only if System Revision >= PERIPH_REV3) .....186
Table 121: Data Mover Descriptor First Doubleword .....................................................................................187
Table 122: Data Mover Descriptor Second Doubleword................................................................................188
Table 123: PCI Base Address Register Use ..................................................................................................205
Table 124: Adaptive Retry Delay ...................................................................................................................218
Table 125: Error Routing Registers ...............................................................................................................229
Table 126: PCI CSR Access Rules................................................................................................................233
Table 127: PCI Interface Configuration Header (Type 0) ..............................................................................236
Table 128: PCI Command Register - Offset 4 Bits [15:0] ..............................................................................240
Table 129: PCI Status Register - Offset 4 Bits [31:16]...................................................................................240
Table 130: PCI Latency Timer - Offset 0C Bits [15:8] ....................................................................................241
Table 131: PCI Cache Line Size - Offset 0C Bits [7:0] ..................................................................................241
Table 132: PCI Timeout Register - Offset 40 Bits [15:0] ................................................................................241
Table 133: PCI Feature Control Register - Offset 40 Bits [31:16] ..................................................................242
Table 134: PCI BAR0 Map Table Entry - Offset 44 - 80 ...............................................................................242
Table 135: PCI Additional Status and Control Register - Offset 88 Bits [31:0] ..............................................242
Table 136: PCI INTA Control Register - Offset 90 Bits [31:0] ........................................................................243
Table 137: PCI Read Host Register - Offset 94 Bits [31:0] ............................................................................243
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