Output Signal Allocations - YASKAWA Sigma-V Series User Manual

<Input signal polarities>
Input signal polarities are as follows when sequence input circuit is connected to a sink circuit. If connected to
a source circuit, polarities are reversed. For details, refer to 3.5.2 Sequence Input Circuit.
Signal
ON
OFF
(4) Checking Input Signals
Input signal status can be checked using the input signal monitor (Un005). As for the input signal monitor
(Un005), refer to 8.4 Monitoring Input Signals.

3.4.2 Output Signal Allocations

Output signals can be allocated to I/O signal connectors (CN1) in accordance with the parameter setting of
Pn50E, Pn50F, Pn510, and Pn512.
(1) Checking Factory Settings
Factory settings can be checked using the following parameters.
Pn50E
Pn50F
Pn510
Level Voltage Level
Low (L) level 0 V
High (H) level 24 V
Allocates /COIN signal to CN1-25, -26.
Allocates /V-CMP signal to CN1-25, -26.
Allocates /TGON signal to CN1-27, -28.
Allocates /S-RDY signal to CN1-29, -30.
Analog
Not to use /CLT signal.
Not to use /VLT signal.
Not to use /BK signal.
Not to use /WARN signal.
Analog
Not to use /NEAR signal.
Reserved (Cannot be changed)
Not to use /PSELA signal.
Reserved (Cannot be changed)
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Analog
3.4 I/O Signal Allocations
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