Clock Generation - Xilinx ZCU106 User Manual

Clock Generation

The ZCU106 board provides fixed and variable clock sources for the XCZU7EV MPSoC.
Table 3-12 lists the source devices for each clock.
Table 3-12: Clock Sources
Clock (Net) Name
Fixed Frequency Clocks
PS_REF_CLK
CLK_74_25
CLK_125
GTR_REF_CLK_SATA
GTR_REF_CLK_USB3
GTR_REF_CLK_DP
Programmable Frequency Clocks
USER_SI570
USER_MGT_SI570
USER_MGT_SMA
HDMI_SI5324_OUT
SFP_SI5328_OUT
Table 3-13 lists the source devices for each clock.
Table 3-13: Clock Connections, Source to XCZU7EV MPSoC
Clock Source Ref.
Des. and Pin
U69.59
U69.45
U69.44
U69.51
U69.50
U69.35
U69.34
U69.31
U69.30
U69.24
U69.23
U42.4
U42.5
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Frequency
33.33 MHz
74.25 MHz
125 MHz
125 MHz
26 MHz
27 MHz
300 MHz (default)
156.25 MHz (default)
User-Provided source
Variable
Variable
Net Name
PS_REF_CLK
CLK_125_P
CLK_125_N
CLK_74_25_P
CLK_74_25_N
GTR_REF_CLK_SATA_P
GTR_REF_CLK_SATA_N
GTR_REF_CLK_USB3_P
GTR_REF_CLK_USB3_N
GTR_REF_CLK_DP_P
GTR_REF_CLK_DP_N
USER_SI570_P
USER_SI570_N
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Chapter 3: Board Component Descriptions
U69 SI5341B clock generator
U42 SI570 I2C PROG. OSC.
U56 SI570 I2C PROG. OSC.
J79 (P)/J80 (N) SMA CONN.
U108 SI5319C clock recovery
U20 SI5328B clock recovery
I/O Standard
(1)
LVDS_25
LVDS_25
LVDS_25
LVDS_25
(2)
(2)
(2)
(2)
(2)
(2)
DIFF_SSTL12
DIFF_SSTL12
Clock Source
XCZU7EV (U1) Pin
R24
H9
G9
D15
D14
P27
P28
M27
M28
M31
M32
AH12
AJ12
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