Pci Express Endpoint Connectivity - Xilinx ZCU106 User Manual

PCI Express Endpoint Connectivity

[Figure 2-1, callout 36]
The 4-lane PCI Express edge connector P3 performs data transfers at the rate of 2.5 GT/s for
Gen1 applications, 5.0 GT/s for Gen2 applications, and 8.0 GT/s for Gen3 applications. The
PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%.
The PCIe clock is routed as a 100Ω differential pair. The XCZU7EV (-2 speed grade) supports
up to Gen3 x8.
The PCIe reference clock input is from the P3 edge connector. It is AC coupled to MPSoC U1
through the MGTREFCLK0 pins of Quad 224. PCIE_CLK_P is connected to U1 pin AB8, and
the _N net is connected to pin AB7. The PCI Express clock connection is shown in
Figure 3-39 and the PCI Express connector is shown in
PCIe lane size is selected by jumper J162 as shown in
selection is 4-lane (J162 pins 2 and 4 jumped).
X-Ref Target - Figure 3-39
P3
PCI Express
Four-Lane
Edge Connector
REFCLK+
REFCLK-
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
OE
A12
GND
A13
PCIE_CLK_Q0_C_P
A14
PCIE_CLK_Q0_C_N
A15
GND
GND
Figure 3-39: PCIe Edge Connector Clock
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Chapter 3: Board Component Descriptions
Figure 3-40.
Figure 3-40. The default lane size
0.1 μf
C339
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
C340
0.1 μf
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