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Xilinx Zynq UltraScale+ User Manual

Mpsoc video codec unit
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Zynq UltraScale+ MPSoC
ZCU106 Video Codec Unit
Targeted Reference Design
User Guide
UG1250 (v2019.1) May 29, 2019

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Summary of Contents for Xilinx Zynq UltraScale+

  • Page 1 Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide UG1250 (v2019.1) May 29, 2019...

  • Page 2: Revision History

    4KP60. Added multi-stream encode/decode support, pipelined MIPI video input, and the HDMI TX video display pipeline. Updated Exported APIs. Limited release. 12/01/2017 2017.2 Initial Xilinx release. Limited release. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019...

  • Page 3: Table Of Contents

    Descriptions ..............79 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Introduction

    Modular and hierarchical architecture (enables partner modules) ° Configurable IP Subsystems ° • System software configuration: Linux symmetric multi-processing (SMP) on the application processing unit (APU) ° Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 6 Chapter 5, Hardware Platform describes the hardware platform of the design including key PS and PL peripherals. • Appendix A, Input Configuration File lists additional resources and references. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 7: Zynq Ultrascale+ Mpsoc Overview

    • Multimedia blocks Graphics processing unit (GPU) Arm Mali-400MP2 ° Video codec (encoder/decoder) unit up to 4K (3840 x 2160) 60 frames per second ° (FPS) Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 8 The APU consists of quad Arm Cortex-A53 cores configured to run in SMP Linux mode. The main task of the application is to configure and control the video pipelines using a Qt v5.9.4 based graphical user application. See Figure 1-2. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 9 IP supports up to eight such layers. The graphics layer is rendered by the GPU. • Audio Capture pipeline to capture audio frames from HDMI-RX, SDI-RX and I2S-RX interfaces. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 10 (zcu106) through PCIe XDMA bridge interface in the PL. The file is passed to the VCU encoder and decoder block for transcoding. The transcoded file is written back to HOST machine using the PCIe XDMA bridge interface read channel. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 11 Figure 1-3: VCU TRD Block Diagram Figure 1-3, except for the VCU Audio design, HDMI pipelines in all other designs exclude Note: Audio Formatter IP and thus do not have audio. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 12: Key Features

    [Ref 3] • SDI Receiver - Blackmagic Design Teranex Mini HDMI to 12G converter • SDI Transmitter - Blackmagic Design Teranex Mini 12G to HDMI converter Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 13 Chapter 1: Introduction Xilinx tools: • Vivado® Design Suite 2019.1 • Xilinx® Software Development Kit (XSDK) 2019.1 [Ref 4] • PetaLinux tools 2019.1 Hardware interfaces and IP: • • Video inputs ° HDMI RX ° MIPI CSI-2 RX ° File source (SD card, SATA and USB 3.0 drives) °...
  • Page 14 Output resolution 4Kp60 (3840 x 2160) — HDMI only ° 4Kp30 (3840 x 2160) — HDMI and DisplayPort ° Native 1080p60 on both DisplayPort and HDMI ° Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 15 Chapter 1: Introduction • Pixel formats NV12 ° NV16 ° XV15 ° XV20 ° Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 16: Chapter 2: Targeted Reference Design Details

    Output Sink: Video and audio are played on HDMI TX ° • Stream 2 Input Source: Video is captured from the MIPI RX Subsystem and audio is captured ° from the I2S RX Subsystem Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 17 Stream-out video. The video captured from the SDI RX Subsystem is encoded and stored in SD cards or USB/SATA drives. The module can Stream-out encoded data through an Ethernet interface. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 18 Detailed step-by-step design and tool flow tutorials for each design module. The rdf0428-zcu106-vcu-trd-2019-1.zip targeted reference design ZIP file is associated with this user guide and available from the Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit Documentation website. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 19: Design Components

    ZCU106 PCIe endpoint, and writes back the transcoded file to the host machine. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 20 Chapter 2: Targeted Reference Design Details • Vivado: Vivado® IP integrator design that integrates the capture, processing (encode/decode), and display pipeline. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 21: Chapter 3: Apu Software Platform

    Linux subsystems. These layers are further grouped by vertical domains which reflect the organization of this chapter: • Video • Audio • Display • Graphics • Accelerator • PCIe Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 22: Software Architecture

    X.Org lib4lsubdev libQt5* gstreamer omx_il libMali libdrm libalsa CtlSW libmediactl Xilinx Alsa Xilinx Mali-400 Xilinx DRM (al5c, al5e, VIPP subdev Framework PCIe and al5r) SDI Tx VCU (Encoder SDI Rx Audio and Decoder) Formatter HDMI Tx HDMI Rx MIPI CSI...
  • Page 23 4. The decoder allocates a decoded frame buffer, reads the bitstream buffer, and writes the decoded frame buffer into memory. 5. The decoder shares the decoded frame buffer using the DMA_BUF framework with the DRM display device. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 24 The main goal of the media framework is to discover the device topology of a video pipeline and to configure it at run time. To achieve this, pipelines are modeled as an oriented graph of building blocks called entities connected through pads. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 25 The grey boxes are video nodes that correspond to Frame Buffer Write channels, in this case write channels (outputs). Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 26 SoCs that often have dedicated hardware blocks for display and graphics. The display pipeline driver responsible for interfacing with the display Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 27 You can develop your application at all three levels: CtrlSW, OMX IL, and GStreamer (Figure 3-4). X-Ref Target - Figure 3-4 GStreamer OMX IL User Space CtrlSW Kernel Space Drivers Hardware HW IP X20054-112718 Figure 3-4: Acceleration Layers Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 28 • Sampling rate: 48 kHz • Sample width: 24 bits per sample • Sample encoding: Little endian • Number of channels: 2 • Supported format: S24_32LE Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 29 PCIe PCIe Software The Xilinx PCI Express DMA (XDMA) IP provides high-performance scatter gather (SG) direct memory access (DMA) via the Endpoint block for PCI Express. Using this IP and the associated drivers and software enable you to generate high-throughput PCIe memory...
  • Page 30 (to access each channel) The vcu_trd_pcie design XDMA is configured in Memory mode and has one read and write channel. For additional information on the XDMA drivers, refer to Xilinx Answer 71435. XDMA Host Application The XDMA host application transfers files from host to client in chunks of buffers using DMA memory-based transfers.
  • Page 31 Video Gamma LUT, VPSS Color Space Converter (CSC), Xilinx Video Processing Subsystem (VPSS Only configuration, 2X configuration), HDMI TX Subsystem, HDMI RX Subsystem, Xilinx Video Pipeline (XVIPP), Mixer, VCU, Xilinx PL sound card, Xilinx Audio Formatter, DisplayPort controller, and the Mali GPU.
  • Page 32 PCIe command line app (pcie_transcode) • PCIe library (pcie_lib) X-Ref Target - Figure 3-8 vcu_qt/vcu_gst_app vgst_err.h vgst_lib.h video.h perfapm.h video.h vcu_gst_lib vcu_video_lib vcu_apm_lib X19933-112718 Figure 3-8: Video Application Interfaces Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 33: Gui Application (Vcu_Qt)

    This determines the number of active video sources. In the current version of the TRD, a maximum of four sources are supported (the default value is one). Figure 3-10 for input settings. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 34 Enc—This option selects encoder in the pipeline. • Enc-Dec—This option selects encode and decode in the pipeline. • Pass-through—This option selects displaying the raw video source. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 35: Demo Mode

    If no source is connected, an error popup displays. If any error returns in any playback, the demo skips and continues to play other pipelines. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 36 This allows a decoder to recognize the requirements to decode that specific stream. H264 supports Baseline, Main, and High profile. In H265, only the Main profile is supported. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 37 If enabled, decreases the vertical search range used for P-frame motion estimation to reduce the bandwidth. GoP Mode Group of Pictures mode. It can be Basic, low_delay_p, or low_delay_b. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 38 A recorded file is saved as source_H26x_rec_<timestamp>ts where source can be HDMI, TPG, or MIPI and codec can be H264/H265. Duration This option specifies the recording time duration. It ranges from 1–3 minutes. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 39 Port Port number of the Ethernet link. The default is 5004. IDR is not user configurable. In the encoder code, the idr value = gop-length. Note: Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 40 Volume Audio volume. Ranges from 0 to 10, default value is 2. Source Available sources are HDMI and I2S Renderer Available renderers are DP and I2S Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 41: Gstreamer Application (Vcu_Gst_App)

    The difference is to manually feed the input configuration and run the pipeline each time, whereas with vcu_qt, the application has to launch only once. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 42: Gstreamer Interface Library (Vcu_Gst_Lib)

    Plug-in libraries get dynamically loaded to support a wide spectrum of codecs, container formats, and input/output drivers. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 43 Table 3-7: GStreamer Plug-ins Plug-in Description v4l2src v4l2src can be used to capture video from V4L2 devices like Xilinx HDMI-RX and TPG. Example pipeline: gst-launch-1.0 v4l2src ! kmssink This pipeline shows the video captured from a /dev/video0 and rendered on a display unit.
  • Page 44 HDMI and one MIPI in multi-stream in 1080p30 resolution. For 8-1080p30 input, the source type can be MIPI or Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 45 HDMI. Here only half of each stream is displayed to showcase eight different streams on a single screen. X-Ref Target - Figure 3-18 X20153-112718 Figure 3-18: Multi-Stream—3 HDMI and 1 MIPI Input Sources @ 1080p60 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 46 In the case of a raw/processed pipeline, the video capture device (v4l2src), video processing accelerator (VCU element), and kmssink plugin use DMABUF framework for sharing buffers between peer elements (see Figure 3-20). Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 47 4. The DisplayPort driver uses the kernel DMA_BUF framework to know the decoder buffer location. 5. The DisplayPort DMA reads the decoded buffer without copying the buffer in kernel memory. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 48: Axi Performance Monitor (Apm) Library (Vcu_Apm_Lib)

    The video capture pipeline present in this design is a TPG/HDMI/MIPI/SDI/SCD Input. It implements a media controller interface that allows you to configure the media pipeline and its sub-devices. The libmediactl and libv4l2subdev libraries provide the following functionality: Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 49 The video_lib library sets the media bus format and video resolution on each sub-device source and sink pad for the entire media pipeline. The formats between pads that are connected through links need to match. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 50: Chapter 4: System Considerations

    (OCM), and reads the boot header. The CSU loads the PMU firmware into the PMU RAM and signals to the PMU to execute the firmware, which Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 51 The graphics layer consists of the GUI and is rendered by the GPU. It overlays certain areas of the video Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 52 4-2). For this design, the relevant parameters are width, height, and stride as the PS display pipeline does not allow for setting an x or y offset. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 53 4 x 1920 = 7,680 bytes. Some DMA engines require the stride to be a power of two to optimize memory accesses. In this design, the stride always equals the width in bytes. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 54: Chapter 5: Hardware Platform

    I2S + Audio RX Encoder LI-IMX274MIPI-FMC Decoder IMX274 MIPI CSI Sensor Source Accerlator SDX Bypass Filter Programmable Processing Accelerator Logic System X19300-051319 Figure 5-1: Hardware Block Diagram Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 55 (rendered by GPU in the graphics layer) and the video layer from memory and sends the data to the HDMI TX Subsystem. The HDMI TX Subsystem processes data and sends it out to an external display device. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 56: Clocking

    TRD. The 125 MHz mig clock is used as PL DDR ref clock. The VCU_DDR4 soft IP generates the 250 MHz user_clk required for processing the data. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 57: Reset

    Interconnect and peripheral reset signals are generated using proc_sys_rst IP in the PL. The VCU Reset in PCIe design is gated with the link_up signal of the PCIe Endpoint block. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 58: Video Pipelines

    The color space format is configurable and set to YUV 4:2:0 in this design. For more Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 59 TMDS data from the video PHY layer. It then extracts the video stream from the HDMI stream and in this design converts it to an Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 60 MIPI CSI-2 IMX274 Subset Demosaic Rx SS Sensor Converter VPSS VPSS Frmbuf Gamma Scaler Write CSI data AXI-S AXI-MM AXI-Lite X20150-042519 Figure 5-5: CSI Video Capture Pipeline Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 61 The Video Processing Subsystem (VPSS) is a collection of video processing IP subcores. This instance uses the VPSS only configuration, which provides scaling, color space conversion, and chroma resampling functionality. The VPSS takes AXI4-Stream input Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 62 The Video Frame Buffer Write IP is used as the Frame Grabber logic, which is designed to allow efficient and high bandwidth access between AXI4-Streaming Video In interfaces to Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 63 Because the data is not timed in non-live mode, video timing is locally generated using the internal Video Timing Controller. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 64 For more information on the DisplayPort controller and the PS-GTR interface, see Chapter 29 PS-GTR Transceivers and Chapter 33 DisplayPort Controller in Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 65 The Video PHY Controller is shared between the HDMI RX and HDMI TX pipelines. Refer HDMI RX Capture Pipeline for more information on the VPHY and its configuration. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 66 Figure 5-9: SDI TX Display Pipeline The SMPTE UHD-SDI Transmitter Subsystem accepts AXI4 Video streams and outputs native SDI streams by using Xilinx transceivers as the physical layer. The Video Mixer enables you to mix video layers and allows mixing up to four streaming or memory layers.
  • Page 67 The AXI DMA with enabled scatter gather (SG) mode provides high-bandwidth direct memory access between memory and the Ethernet 10G Subsystem via AXI interconnect. For more information, see AXI DMA LogiCORE IP Product Guide (PG021) [Ref 17]. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 68 Subsystem and AXI DMA, each shared with the Ethernet 10G input/capture pipeline. Refer Ethernet 10G Input/Capture Pipeline for more information and for the configuration of each component. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 69 AES to PCM. The Audio Engineering Society (AES) standard was developed for the exchange of digital Note: audio signals between professional audio devices. Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 70 • Audio Formatter (see HDMI Audio RX Pipeline) HDMI RX Subsystem IP is available from Xilinx. HDMI 1.4/2.0 Receiver Subsystem v3.1 is the Note: current version as of this printing. Accelerator Processing Pipeline The accelerator processing pipeline is shown in Figure 5-13.
  • Page 71 23]. X-Ref Target - Figure 5-15 SCD Design Pipeline HPM0/1 HDMI Rx VPSS Frmbuf Video Scaler Write Control AXI-Lite AXI-Stream AXI-MM X22775-051719 Figure 5-15: SCD Pipeline Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 72: Address Map

    Chapter 5: Hardware Platform I2S Audio Pipeline The I2S Transmitter and Receiver cores are soft Xilinx IP cores, which make easy to implement inter-IC-sound (I2S) interfaces used to connect audio devices for transmitting and receiving PCM audio. The I2S Transmitter and I2S Receiver cores provide an easy way to interface the I2S based audio DAC/ADC.
  • Page 73 Gamma LUT 0x00_A027_0000 HDMI Receiver subsystem 0x00_A000_0000 HDMI Transmitter subsystem 0x00_A002_0000 128K Video Mixer 0x00_A007_0000 Video Processing Subsystem (VPSS) 0x00_A008_0000 256K Video Processing Subsystem (VPSS-CSC) 0x00_A024_0000 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 74 0x00_A006_2000 SDI TX Frame buffer read 0x00_B001_0000 Video frame buffer read 0x00_A00C_0000 SDI RX Frame buffer write 0x00_B000_0000 Video frame buffer write 0x00_A00D_0000 Video Mixer 0x00_A007_0000 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 75 0x00_A008_0000 256K Video Timing Controller 0x00_A00D_0000 Video Test Pattern Generator (TPG) 0x00_A00E_0000 H.264/H.265 Video Codec Unit (VCU) 0x00_A010_0000 VCU DDR4 Controller 0x48_0000_0000 Video PHY Controller 0x00_A006_0000 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 76: Interrupt Map

    HDMI 1.4/2.0 Transmitter Subsystem v2.0 Video Mixer HDMI Frame Buffer Read HDMI Frame Buffer Write HDMI 1.4/2.0 Receiver Subsystem v2.0 Audio Formatter MM2S 1 Audio Formatter S2MM 1 Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 77 Interrupt ID Audio Formatter mm2s Audio Formatter s2mm Frame Buffer Read Frame Buffer Read Frame Buffer Write Frame Buffer Write SDI Audio Extract SDI RX SDI TX Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 78 Chapter 5: Hardware Platform Table 5-9: Interrupt ID Map for SDI Design (Cont’d) IP Core Interrupt ID Video Mixer Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 79: Appendix A: Input Configuration File

    Options: TPG, HDMI, HDMI_2, HDMI_3, HDMI_4, HDMI_5, HDMI_6, HDMI_7, MIPI, File, SDI, Stream Accelerator Flag: Enables/disables the SDx™ accelerator. For this release, the accelerator works as a bypass filter. Options: True, False Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 80 Exit: Tells the application when input configuration is finished Encoder Configuration: Starting point of encoder configuration Encoder Num: Starting nth encoder configuration Options: 1–8 Encoder Name: Name of encoder Options: AVC, HEVC Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 81 If slice size is defined as well, more slices can be produced to fit the slice size requirement. The default slice value is 8. Options: 4–22 4Kp resolution with HEVC 4–32 4Kp resolution with AVC Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 82 Host IP: The host to send the packets to Options: 192.168.25.89 Port: The port to send the packets to Options: 1024–65534 Exit: Tells the application that streaming configuration is finished Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...
  • Page 83 APM Info: Displays the apm counter number on the console Options: True, False Pipeline Info: Displays pipeline info on the console Options: True, False Exit: Tells the application that trace configuration is finished Zynq UltraScale+ VCU TRD User Guide Send Feedback UG1250 (v2019.1) May 29, 2019 www.xilinx.com...

  • Page 84: Appendix B: Additional Resources And Legal Notices

    Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® integrated design environment (IDE), select Help > Documentation and Tutorials.

  • Page 85: References

    1. GStreamer open source media framework (gstreamer.freedesktop.org/) 2. ZCU106 Evaluation Board User Guide (UG1244) Leopard Imaging Inc. website Xilinx Software Development Kit (XSDK) OpenMAX website Advanced Linux Sound Architecture (ALSA) project homepage 7. Zynq UltraScale+ MPSoC Software Developer Guide (UG1137) 8.

  • Page 86: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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