Uart0 (Mio 18-19); Uart1 (Mio 20-21) - Xilinx ZCU106 User Manual

UART0 (MIO 18-19)

This is the primary Zynq UltraScale+ MPSoC PS-side UART interface and is connected to the
U40 CP2108 USB-to-Quad-UART bridge with port assignments as listed in
PS-side UART0 is accessed through the U40 CP2108 USB-to-Quad-UART bridge port 0. The
CP2108 channel 0 PS-side UART interface circuit is shown in
from XCZU7EV U1 to CP2108 U40 via L/S U54 are listed in
Use SiLabs CP210X VCP driver version 6.7.0 or later for proper USB enumeration as
IMPORTANT:
identified in Table
Table 3-25: CP2108 UART Assignments
CP2108 U40
UART0 PS_UART0 (MIO 18-19)
UART1 PS_UART1 (MIO 20-21)
UART2 PL-UART (HD bank 64)
UART3 U41 system controller UART

UART1 (MIO 20-21)

PS-side UART1 is accessed through the U40 CP2108 USB-to-Quad-UART bridge port 1. The
CP2108 channel 1 PS-side UART interface circuit is shown in
from XCZU7EV U1 to CP2108 U40 via L/S U54 are listed in
X-Ref Target - Figure 3-19
Figure 3-19: CP2108 Channels 0 and 1 PS-Side UART Interface
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
3-27.
Zynq UltraScale+ MPSoC
www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-19. The connections
Table 3-26.
Figure 3-19. The connections
Table 3-26.
X16374-050117
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Table 3-25.
67