Xilinx ZCU106 User Manual page 139

set_propertyPACKAGE_PIN M13
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J10
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K10
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D9
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E9
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E7
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F7
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E8
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F8
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C8
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C9
set_propertyIOSTANDARD
#HPC1 J4
set_propertyPACKAGE_PIN E23
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F23
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN AJ5
set_propertyPACKAGE_PIN AJ6
set_propertyPACKAGE_PIN AK3
set_propertyPACKAGE_PIN AK4
set_propertyPACKAGE_PIN Y7
set_propertyPACKAGE_PIN Y8
set_propertyPACKAGE_PIN B19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN B18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D24
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E24
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K23
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J21
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H24
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J24
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G26
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G25
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H22
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "FMC_HPC0_LA28_P"] ;
LVDS [get_ports "FMC_HPC0_LA28_P"] ;
[get_ports "FMC_HPC0_LA29_N"] ;
LVDS [get_ports "FMC_HPC0_LA29_N"] ;
[get_ports "FMC_HPC0_LA29_P"] ;
LVDS [get_ports "FMC_HPC0_LA29_P"] ;
[get_ports "FMC_HPC0_LA30_N"] ;
LVDS [get_ports "FMC_HPC0_LA30_N"] ;
[get_ports "FMC_HPC0_LA30_P"] ;
LVDS [get_ports "FMC_HPC0_LA30_P"] ;
[get_ports "FMC_HPC0_LA31_N"] ;
LVDS [get_ports "FMC_HPC0_LA31_N"] ;
[get_ports "FMC_HPC0_LA31_P"] ;
LVDS [get_ports "FMC_HPC0_LA31_P"] ;
[get_ports "FMC_HPC0_LA32_N"] ;
LVDS [get_ports "FMC_HPC0_LA32_N"] ;
[get_ports "FMC_HPC0_LA32_P"] ;
LVDS [get_ports "FMC_HPC0_LA32_P"] ;
[get_ports "FMC_HPC0_LA33_N"] ;
LVDS [get_ports "FMC_HPC0_LA33_N"] ;
[get_ports "FMC_HPC0_LA33_P"] ;
LVDS [get_ports "FMC_HPC0_LA33_P"] ;
[get_ports "FMC_HPC1_CLK0_M2C_N"] ;
LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;
[get_ports "FMC_HPC1_CLK0_M2C_P"] ;
LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;
[get_ports "FMC_HPC1_DP0_C2M_N"] ;
[get_ports "FMC_HPC1_DP0_C2M_P"] ;
[get_ports "FMC_HPC1_DP0_M2C_N"] ;
[get_ports "FMC_HPC1_DP0_M2C_P"] ;
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;
[get_ports "FMC_HPC1_LA00_CC_N"] ;
LVDS [get_ports "FMC_HPC1_LA00_CC_N"] ;
[get_ports "FMC_HPC1_LA00_CC_P"] ;
LVDS [get_ports "FMC_HPC1_LA00_CC_P"] ;
[get_ports "FMC_HPC1_LA01_CC_N"] ;
LVDS [get_ports "FMC_HPC1_LA01_CC_N"] ;
[get_ports "FMC_HPC1_LA01_CC_P"] ;
LVDS [get_ports "FMC_HPC1_LA01_CC_P"] ;
[get_ports "FMC_HPC1_LA02_N"] ;
LVDS [get_ports "FMC_HPC1_LA02_N"] ;
[get_ports "FMC_HPC1_LA02_P"] ;
LVDS [get_ports "FMC_HPC1_LA02_P"] ;
[get_ports "FMC_HPC1_LA03_N"] ;
LVDS [get_ports "FMC_HPC1_LA03_N"] ;
[get_ports "FMC_HPC1_LA03_P"] ;
LVDS [get_ports "FMC_HPC1_LA03_P"] ;
[get_ports "FMC_HPC1_LA04_N"] ;
LVDS [get_ports "FMC_HPC1_LA04_N"] ;
[get_ports "FMC_HPC1_LA04_P"] ;
LVDS [get_ports "FMC_HPC1_LA04_P"] ;
[get_ports "FMC_HPC1_LA05_N"] ;
LVDS [get_ports "FMC_HPC1_LA05_N"] ;
[get_ports "FMC_HPC1_LA05_P"] ;
LVDS [get_ports "FMC_HPC1_LA05_P"] ;
[get_ports "FMC_HPC1_LA06_N"] ;
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Appendix B: Master Constraints File Listing
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