Xilinx ZCU106 User Manual page 75

Table 3-29: HDMI Connections to FPGA U1 (Cont'd)
XCZU7EV
Schematic Net Name
(U1) Pin
G8 HDMI_SI5324_LOL
H8 HDMI_SI5324_RST
G14 HDMI_REC_CLOCK_C_P
F13 HDMI_REC_CLOCK_C_N
AD8 HDMI_SI5324_OUT_C_P
AD7 HDMI_SI5324_OUT_C_N
AP4 HDMI_RX0_C_P
AP3 HDMI_RX0_C_N
AN2 HDMI_RX1_C_P
AN1 HDMI_RX1_C_N
AL2 HDMI_RX2_C_P
AL1 HDMI_RX2_C_N
AC10 HDMI_RX_CLK_C_P
AC9 HDMI_RX_CLK_C_N
M8 HDMI_RX_PWR_DET
M10 HDMI_RX_HPD
N12 HDMI_CTL_SCL
P12 HDMI_CTL_SDA
M9 HDMI_RX_SNK_SCL
M11 HDMI_RX_SNK_SDA
Notes:
1. U1 MGT (I/O standards do not apply).
2. TMDS181IRG (U19), SN65DP159 (U94), M24C64-W (U109), and SI5324C (U108).
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Chapter 3: Board Component Descriptions
I/O Standard
Pin
LVCMOS33 18
LVCMOS33 1
LVDS 16
LVDS 17
(1)
28
(1)
29
(1)
B7
(1)
B9
(1)
B4
(1)
B6
(1)
B1
(1)
B3
(1)
B10
(1)
B12
LVCMOS33 3
LVCMOS33 1
LVCMOS33 15
LVCMOS33 16
LVCMOS33 4
LVCMOS33 5
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Connected Component
Name Device
LOL
RST_B
CKIN1_P
SI5324C (U108)
CKIN1_N
CKOUT1_P
CKOUT1_N
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
HDMI bottom
port (P7)
TMDS_DATA2_P
TMDS_DATA2_N
TMDS_CLK_P
TMDS_CLK_N
D Q46
G Q41
SCL_CTL
SDA_CTL
SCL_A
TCA9406DCUR
(U158)
SDA_A
Send Feedback
(2)
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