Appendix B: Master Constraints File Listing; Overview; Zcu106 Board Constraints File Listing - Xilinx ZCU106 User Manual

Master Constraints File Listing

Overview

The master Xilinx design constraints (XDC) file template for the ZCU106 board provides for
designs targeting the ZCU106 evaluation board. Net names in the constraints listed
correlate with net names on the latest ZCU106 evaluation board schematic. Identify the
appropriate pins and replace the net names with net names in the user RTL. See the Vivado
Design Suite User Guide: Using Constraints (UG903)
For detailed I/O standards information required for a particular interface, see the constraint
files generated by tools such as the memory interface generator (MIG) and base system
builder (BSB).
The FMC connectors J5 (HPC0) and J4 (HPC1) are connected to MPSoC banks powered by
the variable voltage V
FMC bank I/O standards must be uniquely defined by each customer.
The XDC file can be accessed on the
IMPORTANT:

ZCU106 Board Constraints File Listing

#CLOCKS
#PS_REF_CLK 33.33 MHz U69 SI5341B
#Other net PACKAGE_PIN R24 - PS_REF_CLK Bank 503 - PS_REF_CLK
#CLK_125 125 MHz U69 SI5341B
set_property PACKAGE_PIN G9
set_property IOSTANDARD
set_property PACKAGE_PIN H9
set_property IOSTANDARD
#CLK_74_25 74.25 MHz U69 SI5341B
set_property PACKAGE_PIN D14
set_property IOSTANDARD
set_property PACKAGE_PIN D15
set_property IOSTANDARD
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
. Because different FMC cards implement different circuitry, the
AJ_FMC
[get_ports "CLK_125_N"] ;
LVDS [get_ports "CLK_125_N"] ;
[get_ports "CLK_125_P"] ;
LVDS [get_ports "CLK_125_P"] ;
[get_ports "CLK_74_25_N"] ;
LVDS [get_ports "CLK_74_25_N"] ;
[get_ports "CLK_74_25_P"] ;
LVDS [get_ports "CLK_74_25_P"] ;
www.xilinx.com
[Ref 9] for more information.
Zynq UltraScale+ ZCU106 Development Kit
Appendix B
website.
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