Xilinx ZCU106 User Manual page 94

FMC HPC_0
Eight MGTs in a common FPGA column are provided by PL-side MGT banks 226 and 227.
Available MGT reference clocks include the FMC defined GBT clocks 0 and 1 for HPC0, and
a programmable Si570 buffered 1-to-2 clock. Additional MGT reference clocks are located
in adjacent MGT banks.
FMC HPC_1
One MGT is provided by PL-side MGT bank 223. Available MGT reference clocks include the
two HDMI associated clocks HDMI_RX_CLK and HDMI_SI5324_OUT. Additional MGT
reference clocks are located in adjacent MGT banks.
SFP+
Two PL-side GTH transceivers in bank 228 are provided for the Quad SFP+ interface.
Available GTH transceiver reference clocks include the FMC defined GBT clock 0 for HPC1
and a jitter attenuated recovered clock from a Si5328. SFP+ modules typically provide an
I2C based control interface. This I2C interface is accessible for each individual SFP+ module
through the I2C multiplexer topology on the ZCU106.
HDMI
Three PL-side GTH transceivers are dedicated for HDMI source and sink. Modes supported
are 4K, 2K at 60 f/s, and 2160p60. External circuitry for interfacing TMDS signals with the
GTH transceivers is required.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Chapter 3: Board Component Descriptions
www.xilinx.com
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