Xilinx ZC702 User Manual
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Xilinx ZC702 User Manual

For the zynq-7000 xc7z020 all programmable soc
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ZC702 Evaluation Board
for the Zynq-7000 XC7Z020
All Programmable SoC
User Guide
UG850 (v1.3) June 4, 2014

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Summary of Contents for Xilinx ZC702

  • Page 1 ZC702 Evaluation Board for the Zynq-7000 XC7Z020 All Programmable SoC User Guide UG850 (v1.3) June 4, 2014...

  • Page 2: Revision History

    Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 3 GND changed to GA0 = 0 = GND in Table 1-28 Table 1-28. The Appendix C Master UCF Listing was replaced with the Xilinx Design Constraints (XDC) file listing. The link in Declaration of Conformity was updated. ZC702 Board User Guide www.xilinx.com...

  • Page 4: Table Of Contents

    Revision History ..............2 Chapter 1: ZC702 Evaluation Board Features Overview .
  • Page 5 ZC702 Board Constraints File Listing........
  • Page 6 Markings ............... . 79 ZC702 Board User Guide www.xilinx.com...

  • Page 7: Chapter 1: Zc702 Evaluation Board Features

    Chapter 1 ZC702 Evaluation Board Features Overview The ZC702 evaluation board for the XC7Z020 All Programmable SoC (AP SoC) provides a hardware environment for developing and evaluating designs targeting the Zynq® XC7Z020-1CLG484C device. The ZC702 board provides features common to many embedded processing systems, including DDR3 component memory, a tri-mode Ethernet PHY, general purpose I/O, and two UART interfaces.
  • Page 8 Power on/off slide switch • Power management with PMBus voltage and current monitoring via TI power controllers • Dual 12-bit 1 MSPS XADC analog-to-digital front end • Configuration options: ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 9: Block Diagram

    Platform cable header JTAG configuration port ° 20-pin PL PJTAG header ° 20-pin PS JTAG header ° Block Diagram The ZC702 board block diagram is shown in Figure 1-1. X-Ref Target - Figure 1-1 Quad SPI JTAG Module DDR3 Memory...

  • Page 10: Board Layout

    Figure 1-2 is for reference only and might not reflect the current revision of the board. The ZC702 board can be damaged by electrostatic discharge (ESD). Follow ESD prevention CAUTION! measures when handling the board. X-Ref Target - Figure 1-2...
  • Page 11 Overview Table 1-1: ZC702 Board Component Descriptions Schematic Reference 0381449 Callout Component Description Notes Designator Page Number Xilinx part number: Zynq-7000 XC7Z020 AP SoC XC7Z020-1CLG484C 4 each 256Mb X 8 SDRAM Micron U66–U69 DDR3 Component Memory, 1 GB 16–19 Technology Inc, MT41J256M8DA-107...

  • Page 12: Feature Descriptions

    Zynq-7000 XC7Z020 AP SoC [Figure 1-2, callout 1] The ZC702 board is populated with the Zynq-7000 XC7Z020-1CLG484C AP SoC. The XC7Z020 AP SoC consists of an SoC-style integrated processing system (PS) and programmable logic (PL) on a single die. ZC702 Board User Guide www.xilinx.com...
  • Page 13 USB, Ethernet, SPI, SD/SDIO, I C, CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 14: Device Configuration

    The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication. ZC702 Board User Guide www.xilinx.com Send Feedback...
  • Page 15 Feature Descriptions The ZC702 board supports these configuration options: • PS Configuration: Quad SPI flash memory • PS Configuration: Processor System Boot from SD Card (J64) • PL Configuration: USB JTAG configuration port (Digilent module) • PL Configuration: Platform cable header J2 and flying lead header J58 JTAG...

  • Page 16: Encryption Key Backup Circuit

    Feature Descriptions Encryption Key Backup Circuit The XC7Z020 AP SoC U1 implements bitstream encryption key technology. The ZC702 board provides the encryption key backup battery circuit shown in Figure 1-5. X-Ref Target - Figure 1-5 VCCAUX 200 mW BAS40-04 4.70K 1%...

  • Page 17: I/O Voltage Rails

    Feature Descriptions I/O Voltage Rails There are four PL I/O banks available on the XC7Z020 AP SoC. The voltages applied to the XC7Z020 AP SoC I/O banks used by the ZC702 board are listed in Table 1-3. Table 1-3: I/O Voltage Rails...
  • Page 18 DQ25 PS_DDR3_DQ26 DQ26 PS_DDR3_DQ27 DQ27 PS_DDR3_DQ28 DQ28 PS_DDR3_DQ29 DQ29 PS_DDR3_DQ30 DQ30 PS_DDR3_DQ31 DQ31 PS_DDR3_DM0 PS_DDR3_DQS0_P DQS0_P PS_DDR3_DQS0_N DQS0_N PS_DDR3_DM1 PS_DDR3_DQS1_P DQS1_P PS_DDR3_DQS1_N DQS1_N PS_DDR3_DM2 PS_DDR3_DQS2_P DQS2_P PS_DDR3_DQS2_N DQS2_N ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 19 U66, U67, U68, U69 PS_DDR3_RAS_B RAS_B U66, U67, U68, U69 PS_DDR3_RESET_B RESET_B U66, U67, U68, U69 PS_DDR3_CS_B CS_B U66, U67, U68, U69 PS_DDR3_ODT U66, U67, U68, U69 PS_VRN PS_VRP ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 20: Quad-Spi Flash Memory

    Pin Number Pin Name Designator VTTVREF_PS VTTVREF_PS The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines Note: documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions v1.8 User Guide (UG586) [Ref 10].

  • Page 21: Usb 2.0 Ulpi Transceiver

    Transceiver at U9 to support a USB connection to the host computer. A USB cable is supplied in the ZC702 Evaluation Kit (Standard-A connector to host computer, Mini-B connector to ZC702 board connector J1). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus.
  • Page 22 Table 1-8: USB 2.0 ULPI Transceiver Connections to the XC7Z020 AP SoC XC7Z020 (U1) Schematic Net Name USB3320 (U9) Pin Pin Name Bank Pin Number PS_MIO36 USB_CLKOUT PS_MIO31 USB_NXT PS_MIO32 USB_DATA0 PS_MIO33 USB_DATA1 PS_MIO34 USB_DATA2 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 23 2-3 = HOST OR OTG MODE VCC3V3 R280 USB HOST POWER 1/10W MIC2025_SOP8 VCC5V0 OUT2 OUT1 C293 LED-RED-SMT 0.1UF 150UF SOP127P500X600_8 TANT UG850_c1_07_030513 Figure 1-7: USB 2.0 ULPI Transceiver ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 24: Sd Card Interface

    [Figure 1-2, callout 5] The ZC702 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose non-volatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk Corporation...

  • Page 25: Programmable Logic Jtag Programming Options

    PS_MIO44 SDIO_DAT0_LS DAT0 PS_MIO43 SDIO_CD_DAT3_LS CD_DAT3 Programmable Logic JTAG Programming Options [Figure 1-2, callout 6] The ZC702 board JTAG chain is shown in Figure 1-9. X-Ref Target - Figure 1-9 SPST Bus Switch SPST Bus Switch JTAG Header N.C. N.C.

  • Page 26: Programmable Logic Jtag Select Switch, Jtag Cable Connector

    Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW10 setting 10 selects the USB-to-JTAG Digilent bridge U23 for configuration over a Standard-A to Micro-B USB cable. DIP switch SW10 setting 11 selects the JTAG 20-pin header at J58. The four JTAG signals TDI, ZC702 Board User Guide www.xilinx.com Send Feedback...

  • Page 27: Fmc Connector Jtag Bypass

    FMC1_HPC_PRSNT_M2C_B signal. Switch U26 adds an attached FMC to the JTAG chain as determined by the FMC2_LPC_PRSNT_M2C_B signal. Clock Generation The ZC702 board provides three clock sources for the XC7Z020 AP SoC. Table 1-11 lists the source devices for each clock.

  • Page 28: System Clock

    Figure 1-11. X-Ref Target - Figure 1-11 VCC2V5 SIT9102 200 MHz Oscillator 0.1 μF 10V SYSCLK_N R168 OUT_B 100Ω 1% SYSCLK_P UG850_c1_11_030513 Figure 1-11: System Clock Source ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 29: Programmable User Clock

    10 MHz to 810 MHz through an I C interface. Power cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz. • Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz) •...

  • Page 30: 10/100/1,000 Mhz Tri-Speed Ethernet Phy

    [Figure 1-2, callout 9] The ZC702 board uses the Marvell Alaska PHY device (88E1116R) at U35 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P2) with built-in magnetics.

  • Page 31: Ethernet Phy Clock Source

    X-Ref Target - Figure 1-14 C322 18pF 50V 25.00 MHz PHY XTAL OUT R246 C333 PHY XTAL IN 18pF 50V UG850_c1_14_030513 Figure 1-14: Ethernet PHY Clock Source ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 32: Usb-To-Uart Bridge

    USB port. The USB cable is supplied in the ZC702 Evaluation Kit (Standard-A end to host computer, Type Mini-B end to ZC702 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC702 board.

  • Page 33: Hdmi Video Output

    [Figure 1-2, callout 13] The ZC702 board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U40. The HDMI output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.
  • Page 34 DSD5 DSD_CLK MCLK GND1 GND2 GND3 I2S0 GND4 I2S1 GND5 I2S2 GND6 I2S3 GND7 SCLK GND8 LRCLK GND9 GND10 R_EXT GND11 R107 UG850_c1_15_030513 Figure 1-15: HDMI Codec Circuit ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 35 HDMI receptacle P1. Table 1-18: ADV7511 to HDMI Receptacle Connections ADV7511 (U40) Net Name HDMI Receptacle P1 Pin HDMI_D0_P HDMI_D0_N HDMI_D1_P HDMI_D1_N HDMI_D2_P HDMI_D2_N ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 36: I2C Bus

    I2C Bus [Figure 1-2, callout 14] The ZC702 board implements a single I C port on the XC7Z020 AP SoC (IIC_SDA_MAIN, IIC_SDA_SCL), which is routed through an TI Semiconductor PCA9548 1-to-8 channel I bus switch (U44). The bus switch can operate at speeds up to 400 kHz.

  • Page 37: Real Time Clock

    Clock counter, alarm and fixed-cycle timer interrupt functions Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual at the Epson Electronics America website [Ref 23]. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 38: I/O Expansion Header

    The 2 x 6 I/O expansion header J54 supports Digilent Pmod Peripheral Modules. 8 pins (IIC_PMOD[0:7]) are connected to the TI TCA6416APWR I C expansion port device U80. See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 24]. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 39: High Speed Can Transceiver

    The TJA1040 (U14) is an advanced high speed Controller Area Network (CAN) transceiver for use in automotive and general industrial applications. It supports the differential bus signal representation described in the international standard for in-vehicle high speed CAN applications (ISO 11898). ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 40 Table 1-21: CAN Transceiver AP SoC Connections TJA1040 (U14) TXS0104E Level Shifter (U3) XC7Z020 AP SoC (U1) Net Name Net Name Low Side Net Bank CAN_TXD CAN_TXD_LS PS_MIO47 CAN_RXD CAN_RXD_LS PS_MIO46 CAN_STB_B CAN_STB_B_LS PS_MIO9 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 41: Status Leds

    Green Power ON UCD9248 Power Controllers U32, U33, U34 DS13 PWRCTL_PWRGOOD Green Power Good (board supply voltages > minimum operating voltage) DS24 PWRCTL1_VCC4A_PG Green FMC1, FMC2 Power Good ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 42: Ethernet Phy User Leds

    UG850_c1_20_030513 Figure 1-20: Ethernet PHY User LEDs User I/O [Figure 1-2, callout 17–28] The ZC702 board provides the following user and general purpose I/O capabilities: • Ten user LEDs (callout 17) PMOD0 0–PMOD0 3 and PMOD1 0–PMOD1 3: DS15–DS22 °...

  • Page 43: User Leds

    [Figure 1-2, callout 17] The ZC702 board supports eight user LEDs connected to XC7Z020 AP SoC Banks 13, 33, 34, and 35 via level-shifters. Note that the LEDs are wired in parallel with headers J63 (PMOD1) and J62 (PMOD2). These headers are described in...
  • Page 44 460 mW 460 mW VCC3V3 VCC3V3 DS23 DS12 VCCMIO (1.8V) R416 R393 20.5K 0.1W 0.1W 0.1W NDS331N NDS331N PS_LED1 PS_MIO8_LED0 460 mW 460 mW UG850_c1_21_030513 Figure 1-21: User LEDs ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 45: User Pushbuttons

    Table 1-24: User Pushbutton Connections to XC7Z020 AP SoC U1 XC7Z020 AP SoC (U1) Pin Net Name Pushbutton and Pin Reference GPIO_SW_N SW5.3 (Left switch) GPIO_SW_S SW7.3 (Right switch) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 46: Gpio Dip Switch

    GPIO DIP switch connections to XC7Z020 AP SoC U1. Table 1-25: GPIO DIP Switch Connections to XC7Z020 AP SoC at U1 XC7Z020 AP SoC (U1) Pin Net Name DIP Switch SW12 Pin GPIO_DIP_SW0 GPIO_DIP_SW1 ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 47: User Ps Switches

    SW14.4 and SW15.2 User PMOD GPIO Headers [Figure 1-2, callout 28] The ZC702 board supports two GPIO headers J62 and J63. The PMOD nets connected to these headers are dual-purpose, with the User LEDs, page 43 wired in parallel to the header pins.

  • Page 48: Switches

    [Ref 9] for information about the PS PJTAG functionality. Switches [Figure 1-2, callout 22–26] The ZC702 board includes a power and a configuration switch: • Power On/Off slide switch SW11 (callout 26) • SW4 (FPGA_PROG_B), active-Low pushbutton (callout 22) ZC702 Board User Guide www.xilinx.com...

  • Page 49: Power On/Off Slide Switch

    Do NOT plug a PC ATX power supply 6-pin connector into J60 on the ZC702 board. The ATX CAUTION! 6-pin connector has a different pinout than J60. Connecting an ATX 6-pin connector into J60 will damage the ZC702 board and void the board warranty.

  • Page 50: Ps Power-On And System Reset Pushbuttons

    It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal. Depressing and then releasing pushbutton SW2 causes PS_SRST_B_SW to strobe low. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 51: Fpga Mezzanine (Fmc) Card Interface

    (LPC) connectors at J3 and J4. Both connectors use a 10 x 40 form factor that is partially populated with 160 pins. The connectors are keyed so that a the mezzanine card faces away from the ZC702 board when connected.
  • Page 52 FMC1_LPC_LA14_N FMC1_LPC_LA13_P FMC1_LPC_LA18_CC_P FMC1_LPC_LA13_N FMC1_LPC_LA18_CC_N FMC1_LPC_LA17_CC_P FMC1_LPC_LA27_P FMC1_LPC_LA17_CC_N FMC1_LPC_LA27_N FMC1_LPC_LA23_P FMC1_LPC_IIC_SCL FMC1_LPC_LA23_N FMC1_LPC_IIC_SDA FMC1_LPC_LA26_P GA0 = 0 = GND FMC1_LPC_LA26_N VCC12_P FMC1_LPC_TCK_BUF VCC12_P FMC_TDI_BUF VCC3V3 FMC1_LPC_TDO_FMC2_LPC_TDI VCC3V3 FMC1_LPC_TMS_BUF ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 53 FMC1_LPC_LA20_P FMC1_LPC_LA15_P FMC1_LPC_LA20_N FMC1_LPC_LA15_N FMC1_LPC_LA22_P FMC1_LPC_LA19_P FMC1_LPC_LA22_N FMC1_LPC_LA19_N FMC1_LPC_LA25_P FMC1_LPC_LA21_P FMC1_LPC_LA25_N FMC1_LPC_LA21_N FMC1_LPC_LA29_P FMC1_LPC_LA24_P FMC1_LPC_LA29_N FMC1_LPC_LA24_N FMC1_LPC_LA31_P FMC1_LPC_LA28_P FMC1_LPC_LA31_N FMC1_LPC_LA28_N FMC1_LPC_LA33_P FMC1_LPC_LA30_P FMC1_LPC_LA33_N FMC1_LPC_LA30_N VADJ FMC1_LPC_LA32_P FMC1_LPC_LA32_N VADJ ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 54 VCC12_P FMC2_LPC_TCK_BUF VCC12_P FMC1_LPC_TDO_FMC2_LPC_TDI VCC3V3 FMC2_LPC_TDO_FPGA_TDI VCC3V3 FMC2_LPC_TMS_BUF GA0 = 0 = GND VCC3V3 VCC3V3 VCC3V3 FMC2_LPC_CLK1_M2C_P FMC2_LPC_CLK1_M2C_N FMC2_LPC_PRSNT_M2C_B FMC2_LPC_LA00_CC_P FMC2_LPC_CLK0_M2C_P FMC2_LPC_LA00_CC_N AA19 FMC2_LPC_CLK0_M2C_N AA18 FMC2_LPC_LA03_P AA16 FMC2_LPC_LA02_P ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 55: Power Management

    1-2, callout 25] TheZC702 PCB layout and power system design meets the recommended criteria described in the Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933) [Ref 14]. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 56 Feature Descriptions The ZC702 board power distribution diagram is shown in Figure 1-29. X-Ref Target - Figure 1-29 12 V Power Controller 1 (Core) PMBus Address 52 Switching Regulator VCCINT 1.0V at 10A VCCPINT Switching Regulator 1.0V at 10A Switching Regulator VCCAUX 1.8V at 10A...
  • Page 57 Feature Descriptions The ZC702 board uses power regulators and a PMBus compliant system controller from Texas Instruments to supply core and auxiliary voltages as listed in Table 1-30. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.

  • Page 58: Vadj Voltage Control

    Feature Descriptions VADJ Voltage Control The VADJ rail is set to 2.5V. When the ZC702 board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J12 is sampled by the TI UCD9248 controller U33. If a jumper is installed on J12 signal FMC_VADJ_ON_B is held low, and the TI controller U33 energizes the VADJ rail at power on.
  • Page 59 1.15 Notes: 1. The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut down if the value is exceeded. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 60: Cooling Fan

    1-30. X-Ref Target - Figure 1-30 VCC12_P UG850_c1_30_030513 Figure 1-30: Cooling Fan Circuit More information about the power system components used by the ZC702 board are available from the Texas Instruments digital power website [Ref 26]. ZC702 Board User Guide www.xilinx.com...

  • Page 61: Xadc Analog-To-Digital Converter

    100Ω UG850_c1_31_030513 Figure 1-31: XADC Block Diagram The ZC702 board supports both the internal XC7Z020 AP SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available. ZC702 Board User Guide www.xilinx.com...
  • Page 62 Digital I/O. These pins should come from the same bank. These I/Os XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18 should not be shared with other functions because they are required to support three-state operation. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 63: Appendix A: Default Switch And Jumper Settings

    [Figure 1-2, callout 24] Default jumper positions are listed in Table A-2. Table A-2: Default Jumper Settings Jumper Function Default Position HDR_1 X 2 CFGBVS short to GND ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 64 ETHERNET PHY HDR NONE USB 2.0 MODE USB 2.0 J1 ID SEL USB 2.0 J1 VBUS CAP SEL USB 2.0 J1 GND SEL XADC_VREP SEL XADC_VCC SEL XADC_VREF SOURCE SEL ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 65: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC702 board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface,...

  • Page 66: Overview

    The ZC702 Xilinx Design Constraints (XDC) template provides for designs targeting the ZC702 board. Net names in the constraints listed in the file correlate with net names on the latest ZC702 board schematic. Users must identify the appropriate pins and replace the net names below with net names in the user RTL.
  • Page 67 ZC702 Board Constraints File Listing set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA01_CC_N] set_property PACKAGE_PIN N19 [get_ports FMC1_LPC_LA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA01_CC_P] set_property PACKAGE_PIN L22 [get_ports FMC1_LPC_LA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA02_N] set_property PACKAGE_PIN L21 [get_ports FMC1_LPC_LA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA02_P]...
  • Page 68 ZC702 Board Constraints File Listing set_property PACKAGE_PIN P15 [get_ports FMC1_LPC_LA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA16_N] set_property PACKAGE_PIN N15 [get_ports FMC1_LPC_LA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA16_P] set_property PACKAGE_PIN B20 [get_ports FMC1_LPC_LA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA17_CC_N] set_property PACKAGE_PIN B19 [get_ports FMC1_LPC_LA17_CC_P]...
  • Page 69 ZC702 Board Constraints File Listing set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA30_P] set_property PACKAGE_PIN A17 [get_ports FMC1_LPC_LA31_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA31_N] set_property PACKAGE_PIN A16 [get_ports FMC1_LPC_LA31_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA31_P] set_property PACKAGE_PIN B22 [get_ports FMC1_LPC_LA32_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC1_LPC_LA32_N]...
  • Page 70 ZC702 Board Constraints File Listing set_property PACKAGE_PIN U15 [get_ports FMC2_LPC_LA09_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA09_P] set_property PACKAGE_PIN Y21 [get_ports FMC2_LPC_LA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA10_N] set_property PACKAGE_PIN Y20 [get_ports FMC2_LPC_LA10_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA10_P] set_property PACKAGE_PIN AA14 [get_ports FMC2_LPC_LA11_N]...
  • Page 71 ZC702 Board Constraints File Listing set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA24_N] set_property PACKAGE_PIN U6 [get_ports FMC2_LPC_LA24_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA24_P] set_property PACKAGE_PIN AB12 [get_ports FMC2_LPC_LA25_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA25_N] set_property PACKAGE_PIN AA12 [get_ports FMC2_LPC_LA25_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC2_LPC_LA25_P]...
  • Page 72 ZC702 Board Constraints File Listing set_property PACKAGE_PIN AA22 [get_ports HDMI_R_D3] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D3] set_property PACKAGE_PIN V19 [get_ports HDMI_R_D4] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D4] set_property PACKAGE_PIN V18 [get_ports HDMI_R_D5] set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D5] set_property PACKAGE_PIN V20 [get_ports HDMI_R_D6]...
  • Page 73 ZC702 Board Constraints File Listing set_property IOSTANDARD LVCMOS25 [get_ports PMOD2_0_LS] set_property PACKAGE_PIN W10 [get_ports PMOD2_1_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD2_1_LS] set_property PACKAGE_PIN P18 [get_ports PMOD2_2_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD2_2_LS] set_property PACKAGE_PIN P17 [get_ports PMOD2_3_LS] set_property IOSTANDARD LVCMOS25 [get_ports PMOD2_3_LS]...

  • Page 74: Appendix D: Board Specifications

    Width: 7.750 in. (19.685 cm) Length: 7.150 in. (18.161 cm) Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C Humidity 10% to 90% non-condensing Operating Voltage +12 V ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 75: Appendix E: Additional Resources

    Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the ZC702 board and its documentation is available on the following websites. ZC702 Evaluation Kit...
  • Page 76 21. Marvell Semiconductor: www.marvell.com (88E1116R) 22. Analog Devices: www.analog.com/en/index.html (ADV7511KSTZ-P, ADP123) 23. Epson Electronics America: www.eea.epson.com www.eea.epson.com/portal/pls/portal/docs/1/1413485.PDF (RTC-8564JE) 24. Digilent: www.digilentinc.com www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 (Pmod Peripheral Modules) 25. NXP Semiconductors: ics.nxp.com (TJA01040) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...
  • Page 77 27. Texas Instruments EVM USB-TO-GPIO: www.ti.com/xilinx_usb. 28. Texas Instruments TI Fusion Digital Power Designer GUI, downloadable from: http://www.ti.com/fusion-gui 29. Samtec: www.samtec.com. (SEAF series connectors) 30. Integrated Device Technology: www.idt.com (ICS844021I) ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

  • Page 78: Appendix F: Regulatory And Compliance Information

    Regulatory and Compliance Information This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the ZC702 board master answer record concerning the CE requirements for the PC Test Environment: www.xilinx.com/support/answers/47864.htm...

  • Page 79: Safety

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. ZC702 Board User Guide www.xilinx.com Send Feedback UG850 (v1.3) June 4, 2014...

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