Xilinx ZCU106 User Manual page 41

Table 3-7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the
default shunt positions for USB 2.0 high speed on-the-go (OTG) mode.
Table 3-7: USB Jumper Settings
Header Function
J110 CVBUS select
J96 USB 3.0 A
The connections between the USB 2.0 PHY at U116 and the XCZU7EV MPSoC are listed in
Table 3-8.
Table 3-8: USB 2.0 ULPI Transceiver Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin
U117.4
H31
G30
G29
G33
G34
H29
G31
H32
H33
H34
J29
J30
Notes:
1. PS_POR_B (U1.M24) or PS_MODE1 (DIP SW6.2) or PB SW2 drive U116 RST_B via OR gate U117.
2. These nets are 30Ω series resistor coupled.
The shield for the USB 3.0 A connector (J96) can be tied to GND by a jumper on header J112
Note:
pins 2-3 (default). The USB shield can optionally be connected through a capacitor to GND by
installing a capacitor (body size 0402) at location C887 and jumping pins 1-2 on header J112.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Shunt Position
ON = Device mode (1 µF)
OFF = Host mode (120 µF) and source of bus
power
Position 1-2 = Shield floating (DNP C887 pads)
Position 2-3 = Shield connected to GND
Net Name
(1)
ULPI0_RST_B
(2)
MIO58_USB_STP
MIO53_USB_DIR
MIO52_USB_CLK
MIO55_USB_NXT
(2)
MIO56_USB_DATA0
(2)
MIO57_USB_DATA1
(2)
MIO54_USB_DATA2
(2)
MIO59_USB_DATA3
(2)
MIO60_USB_DATA4
(2)
MIO61_USB_DATA5
(2)
MIO62_USB_DATA6
(2)
MIO63_USB_DATA7
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Chapter 3: Board Component Descriptions
VBUS load capacitance
USB3320 U116
Pin #
27
29
31
1
2
3
4
5
6
7
9
10
13
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Notes
Pin Name
RESET_B
STP
DIR
CLKOUT
NXT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
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