Quad Spi Flash Memory (Mio 0-12) - Xilinx ZCU106 User Manual

Table 3-5: MIO Peripheral Mapping (Cont'd)
MIO[0:25] Bank 500
18 UART0
19 UART0
20 UART1
21 UART1
22 GPIO
23 GPIO
24 CAN1
25 CAN1
Quad SPI Flash Memory (MIO 0–12)
[Figure 2-1, callout 3]
The Micron dual MT25QU512ABB8ESF serial NOR flash Quad SPI flash memories can hold
the boot image for the MPSoC system. To achieve higher performance, two Quad SPI flash
memory devices are connected in parallel and provide an 8-bit data bus for boot and
configuration. This interface is used to support QSPI32 boot mode as defined in the Zynq
UltraScale+ MPSoC Technical Reference Manual (UG1085)
The dual Quad SPI flash memory located at U119/U120 provides 1 Gb of non-volatile
storage that can be used for configuration and data storage.
• Part number: MT25QU512ABB8ESF-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 8 bits
• Data rate: various depending on single, dual, or quad mode
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
MIO[26:51] Bank 501
44 SD1
45 SD1
46 SD1
47 SD1
48 SD1
49 SD1
50 SD1
51 SD1
www.xilinx.com
Chapter 3: Board Component Descriptions
MIO[52:77] Bank 502
70
71
72
73
74
75
76
77
[Ref 2].
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GEM3
GEM3
GEM3
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GEM3
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