Clock Generation - Xilinx KCU116 User Manual

Clock Generation

[Figure 2-1, callout 6]
The KCU116 evaluation board provides eight clock sources to the XCKU5P device as listed in
Table 3-5.
Table 3‐5: KCU116 Board Clock Sources
Clock Name
System clock 300 MHz
System clock 125 MHz
EMC clock 90 MHz
System control clock 33.333 MHz
User MGT clock 10 MHz–810 MHz
User SMA clock
Jitter attenuated clock
Video clock 74.25 MHz
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Clock Ref. Des.
Silicon Labs Si5335A 1.8V LVDS any frequency quad
U170 clock generator CLK0. See
and SYSCLK_300_N).
Silicon Labs Si5335A 1.8V LVDS any frequency quad
U170
clock generator CLK1. See
Silicon Labs Si5335A 1.8V LVCMOS single-ended any
U170 frequency quad clock generator CLK2. See
(FPGA_EMCCLK).
Silicon Labs Si5335A 1.8V LVCMOS single-ended any
U170 frequency quad clock generator CLK3. See
(SYSCTLR_CLK).
Silicon Labs Si570 3.3V LVDS I
oscillator, 156.250 MHz default.
U56
(USER_MGT_SI570_CLOCK_P and
USER_MGT_SI570_CLOCK_N).
User clock input SMAs. See
J168(P), J169(N)
(USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).
Silicon Labs Si5328C LVDS precision clock
U20 multiplier/jitter attenuator. See
(SFP_SI5328_OUT_P and SFP_SI5328_OUT_N).
Silicon Labs Si511 3.3V LVDS fixed frequency oscillator.
U179
See Video Clock
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Chapter 3: Board Component Descriptions
Description
System Clock
System Clock
2
C programmable
User SMA Clock
Jitter Attenuated Clock
(CLK_74_25_P and CLK_74_25_N).
Send Feedback
(SYSCLK_300_P
(CLK_125MHZ).
System Clock
System Clock
28