Xilinx ZCU106 User Manual page 97

Table 3-39: GTH Transceiver Bank 225 Interface Connections
XCZU7EV XCZU7EV Pin
(U1) Pin Name
AC6 MGTHTXP0
AC5 MGTHTXN0
AC2 MGTHRXP0
AC1 MGTHRXN0
AA6 MGTHTXP1
AA5 MGTHTXN1
AB4 MGTHRXP1
AB3 MGTHRXN1
Y4 MGTHTXP2
Y3 MGTHTXN2
AA2 MGTHRXP2
AA1 MGTHRXN2
W6 MGTHTXP3
W5 MGTHTXN3
W2 MGTHRXP3
W1 MGTHRXN3
Y8 MGTREFCLK0P
Y7 MGTREFCLK0N
W10 MGTREFCLK1P
W9 MGTREFCLK1N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Schematic Net Name
(1)
SDI_MGT_TX_P
(1)
SDI_MGT_TX_N
(1)
SDI_MGT_RX_P
(1)
SDI_MGT_RX_N
SMA_MGT_TX_P
SMA_MGT_TX_N
(1)
SMA_MGT_RX_C_P
(1)
SMA_MGT_RX_C_N
SFP0_TX_P
SFP0_TX_N
SFP0_RX_P
SFP0_RX_N
SFP1_TX_P
SFP1_TX_N
SFP1_RX_P
SFP1_RX_N
FMC_HPC1_GBTCLK0_M2C_C_P
FMC_HPC1_GBTCLK0_M2C_C_N
SFP_SI5328_OUT_C_P
SFP_SI5328_OUT_C_N
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Chapter 3: Board Component Descriptions
Connected To
(2)
Pin
Pin Name
No.
3 SDI_P
4 SDI_N
20 SDO0_P
19 SDO0_N
1 SIG
1 SIG
1 SIG
1 SIG
18 TD_P
19 TD_N
13 RD_P
12 RD_N
18 TD_P
19 TD_N
13 RD_P
12 RD_N
(1)
D4 GBTCLK0_M2C_P
(1)
D5 GBTCLK0_M2C_N
(1)
28 CKOUT1_P
(1)
29 CKOUT1_N
Device
M23145G_14PG
re-clocker
M23554G_14PG
re-clocker
MGT SMA J72
MGT SMA J42
MGT SMA J74
MGT SMA J73
SFP0 connector P1
SFP0 connector P2
FMC HPC1 J4
SI5328B U20
97
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