Hdmi Clock Recovery - Xilinx ZCU106 User Manual

HDMI Clock Recovery

[Figure 2-1, callout 41]
The ZCU106 board includes a Silicon Labs Si5319C jitter attenuator U108 (2 kHz – 945 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 67
(HDMI_REC_CLOCK_C_P, pin G14 and HDMI_REC_CLOCK_C_N, pin F13) for jitter attenuation.
The jitter attenuated clock (HDMI_SI5324_OUT_C_P (U108 pin 28), HDMI_SI5324_OUT_C_N
(U108 pin 29) is then routed as a series capacitor coupled reference clock to GTH Quad 223
inputs MGTREFCLK0P (U1 pin AD8) and MGTREFCLK0N (U1 pin AD7).
The Si5319C jitter attenuator is used to generate the reference clock for the HDMI
transmitter subsystem. When the HDMI transmitter is used in standalone mode, the
Si5319C operates in free-running mode and uses an external oscillator as the reference.
When the HDMI transmitter is used in pass-through mode, the Si5319C generates a
jitter-attenuated reference clock to drive the HDMI transmitter subsystem with a
phase-aligned version of the HDMI Rx subsystem HMDI Rx TMDS clock, so that they are
phase aligned. The SI5319C clock and jitter enable functions are controlled by HDMI IP.
Communication with the SI5319C is available over the HDMI_CTL_SDA/SCL bus connected
to the XCZU7EV MPSoC U1 PL bank 87. The jitter attenuated clock circuit is shown in
Figure 3-26.
The Silicon Labs Si5319C U108 pin 1 reset net HDMI_SI5324_RST must be driven High to
IMPORTANT:
enable the device. U108 pin 1 net HDMI_SI5324_RST is connected to FPGA U1 bank 87 pin H8.
X-Ref Target - Figure 3-26
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Figure 3-26: HDMI Interface Clock Recovery
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Chapter 3: Board Component Descriptions
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