Xilinx ZCU106 User Manual page 142

set_property IOSTANDARD
set_property PACKAGE_PIN D2
set_property IOSTANDARD
set_property PACKAGE_PIN C2
set_property IOSTANDARD
set_property PACKAGE_PIN C3
set_property IOSTANDARD
set_property PACKAGE_PIN B3
set_property IOSTANDARD
set_property PACKAGE_PIN C4
set_property IOSTANDARD
set_property PACKAGE_PIN B4
set_property IOSTANDARD
set_property PACKAGE_PIN E4
set_property IOSTANDARD
set_property PACKAGE_PIN D4
set_property IOSTANDARD
set_property PACKAGE_PIN E5
set_property IOSTANDARD
set_property PACKAGE_PIN F6
set_property IOSTANDARD
set_property PACKAGE_PIN D5
set_property IOSTANDARD
set_property PACKAGE_PIN D6
set_property IOSTANDARD
set_property PACKAGE_PIN A5
set_property IOSTANDARD
set_property PACKAGE_PIN B5
set_property IOSTANDARD
set_property PACKAGE_PIN F4
set_property IOSTANDARD
set_property PACKAGE_PIN F5
set_property IOSTANDARD
set_property PACKAGE_PIN E2
set_property IOSTANDARD
set_property PACKAGE_PIN E3
set_property IOSTANDARD
set_property PACKAGE_PIN A2
set_property IOSTANDARD
set_property PACKAGE_PIN K8
set_property IOSTANDARD
#GPIO
#PUSHBUTTON SWITCHES
set_property PACKAGE_PIN AG13
set_property IOSTANDARD
set_property PACKAGE_PIN AP20
set_property IOSTANDARD
set_property PACKAGE_PIN AC14
set_property IOSTANDARD
set_property PACKAGE_PIN AK12
set_property IOSTANDARD
set_property PACKAGE_PIN AL10
set_property IOSTANDARD
#CPU_RESET PUSHBUTTON
set_property PACKAGE_PIN G13
set_property IOSTANDARD
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
LVCMOS33 [get_ports "TRACEDATA7"] ;
[get_ports "TRACEDATA8"] ;
LVCMOS33 [get_ports "TRACEDATA8"] ;
[get_ports "TRACEDATA9"] ;
LVCMOS33 [get_ports "TRACEDATA9"] ;
[get_ports "TRACEDATA10"] ;
LVCMOS33 [get_ports "TRACEDATA10"] ;
[get_ports "TRACEDATA11"] ;
LVCMOS33 [get_ports "TRACEDATA11"] ;
[get_ports "TRACEDATA12"] ;
LVCMOS33 [get_ports "TRACEDATA12"] ;
[get_ports "TRACEDATA13"] ;
LVCMOS33 [get_ports "TRACEDATA13"] ;
[get_ports "TRACEDATA14"] ;
LVCMOS33 [get_ports "TRACEDATA14"] ;
[get_ports "TRACEDATA15"] ;
LVCMOS33 [get_ports "TRACEDATA15"] ;
[get_ports "TRACEDBGRQ"] ;
LVCMOS33 [get_ports "TRACEDBGRQ"] ;
[get_ports "TRACESRST_B"] ;
LVCMOS33 [get_ports "TRACESRST_B"] ;
[get_ports "TRACETDO"] ;
LVCMOS33 [get_ports "TRACETDO"] ;
[get_ports "TRACERTCK"] ;
LVCMOS33 [get_ports "TRACERTCK"] ;
[get_ports "TRACETCK"] ;
LVCMOS33 [get_ports "TRACETCK"] ;
[get_ports "TRACETMS"] ;
LVCMOS33 [get_ports "TRACETMS"] ;
[get_ports "TRACETDI"] ;
LVCMOS33 [get_ports "TRACETDI"] ;
[get_ports "TRACETRST_B"] ;
LVCMOS33 [get_ports "TRACETRST_B"] ;
[get_ports "TRACECLKA"] ;
LVCMOS33 [get_ports "TRACECLKA"] ;
[get_ports "TRACEDBGACK"] ;
LVCMOS33 [get_ports "TRACEDBGACK"] ;
[get_ports "TRACEEXTTRIG"] ;
LVCMOS33 [get_ports "TRACEEXTTRIG"] ;
[get_ports "TRACECTL"] ;
LVCMOS33 [get_ports "TRACECTL"] ;
[get_ports "GPIO_SW_N"] ;
LVCMOS12 [get_ports "GPIO_SW_N"] ;
[get_ports "GPIO_SW_S"] ;
LVCMOS12 [get_ports "GPIO_SW_S"] ;
[get_ports "GPIO_SW_E"] ;
LVCMOS12 [get_ports "GPIO_SW_E"] ;
[get_ports "GPIO_SW_W"] ;
LVCMOS12 [get_ports "GPIO_SW_W"] ;
[get_ports "GPIO_SW_C"] ;
LVCMOS12 [get_ports "GPIO_SW_C"] ;
[get_ports "CPU_RESET"] ;
LVCMOS18 [get_ports "CPU_RESET"] ;
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Appendix B: Master Constraints File Listing
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