Xilinx ZCU106 User Manual page 134

set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ20"] ;
set_propertyPACKAGE_PIN AK18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ21"] ;
set_propertyPACKAGE_PIN AL16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ22"] ;
set_propertyPACKAGE_PIN AL18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ23"] ;
set_propertyPACKAGE_PIN AP13
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ24"] ;
set_propertyPACKAGE_PIN AP16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ25"] ;
set_propertyPACKAGE_PIN AP15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ26"] ;
set_propertyPACKAGE_PIN AN16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ27"] ;
set_propertyPACKAGE_PIN AN13
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ28"] ;
set_propertyPACKAGE_PIN AM18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ29"] ;
set_propertyPACKAGE_PIN AN17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ30"] ;
set_propertyPACKAGE_PIN AN18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ31"] ;
set_propertyPACKAGE_PIN AB19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ32"] ;
set_propertyPACKAGE_PIN AD19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ33"] ;
set_propertyPACKAGE_PIN AC18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ34"] ;
set_propertyPACKAGE_PIN AC19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ35"] ;
set_propertyPACKAGE_PIN AA20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ36"] ;
set_propertyPACKAGE_PIN AE20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ37"] ;
set_propertyPACKAGE_PIN AA19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ38"] ;
set_propertyPACKAGE_PIN AD20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ39"] ;
set_propertyPACKAGE_PIN AF22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ40"] ;
set_propertyPACKAGE_PIN AH21
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ41"] ;
set_propertyPACKAGE_PIN AG19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ42"] ;
set_propertyPACKAGE_PIN AG21
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ43"] ;
set_propertyPACKAGE_PIN AE24
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ44"] ;
set_propertyPACKAGE_PIN AG20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ45"] ;
set_propertyPACKAGE_PIN AE23
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ46"] ;
set_propertyPACKAGE_PIN AF21
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ47"] ;
set_propertyPACKAGE_PIN AL22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ48"] ;
set_propertyPACKAGE_PIN AJ22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ49"] ;
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Appendix B: Master Constraints File Listing
[get_ports "DDR4_DQ21"] ;
[get_ports "DDR4_DQ22"] ;
[get_ports "DDR4_DQ23"] ;
[get_ports "DDR4_DQ24"] ;
[get_ports "DDR4_DQ25"] ;
[get_ports "DDR4_DQ26"] ;
[get_ports "DDR4_DQ27"] ;
[get_ports "DDR4_DQ28"] ;
[get_ports "DDR4_DQ29"] ;
[get_ports "DDR4_DQ30"] ;
[get_ports "DDR4_DQ31"] ;
[get_ports "DDR4_DQ32"] ;
[get_ports "DDR4_DQ33"] ;
[get_ports "DDR4_DQ34"] ;
[get_ports "DDR4_DQ35"] ;
[get_ports "DDR4_DQ36"] ;
[get_ports "DDR4_DQ37"] ;
[get_ports "DDR4_DQ38"] ;
[get_ports "DDR4_DQ39"] ;
[get_ports "DDR4_DQ40"] ;
[get_ports "DDR4_DQ41"] ;
[get_ports "DDR4_DQ42"] ;
[get_ports "DDR4_DQ43"] ;
[get_ports "DDR4_DQ44"] ;
[get_ports "DDR4_DQ45"] ;
[get_ports "DDR4_DQ46"] ;
[get_ports "DDR4_DQ47"] ;
[get_ports "DDR4_DQ48"] ;
[get_ports "DDR4_DQ49"] ;
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