User I2C0 Receptacle - Xilinx ZCU106 User Manual

Table 3-34 lists the connections between the XCZU7EV MPSoC and the prototype header.
Table 3-34: Prototype Header J3 Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin
L14
K13
K14
J14
K12
J11
L12
L11
G23
G24

User I2C0 Receptacle

[Figure 2-1, callout 21]
The ZCU106 evaluation board supports a PMOD 2X6 receptacle (right-angle female) J160.
Figure 3-33 shows the I2C0 PMOD receptacle J160. The I2C0 nets are a branch of the I2C0
main bus (see Figure 3-17, page 61
X-Ref Target - Figure 3-33
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
L6P_AD6P_64_P
L6N_AD6N_64_N
L5P_AD14P_64_P
L5N_AD14N_64_N
L4P_AD7P_64_P
L4N_AD7N_64_N
L3P_AD15P_64_P
L3N_AD15N_64_N
L14P_HDGC_65_P
L14N_HDGC_65_N
and I2C0 (MIO 14-15), page 60
Figure 3-33: J160 PMOD I2C0 Right-Angle Receptacle
www.xilinx.com
Chapter 3: Board Component Descriptions
I/O Standard Prototype Header J3 Pin
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
for more details).
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