Fmc Connector Jtag Bypass; Clock Generation - Xilinx ZC702 User Manual

Table 1-10: Switch SW10 JTAG Configuration Option Settings
Configuration Source
None
Digilent USB-to-JTAG interface U23
(2)
Cable connector J2
JTAG header J58
Notes:
1. 0 = open, 1 = closed
2. Default switch setting

FMC Connector JTAG Bypass

When an FPGA mezzanine card (FMC) is attached to J3 or J4 it is automatically added to the
JTAG chain through electronically controlled single-pole single-throw (SPST) switches U25
and U26. The SPST switches are normally closed and transition to an open state when an
FMC is attached. Switch U25 adds an attached FMC to the JTAG chain as determined by the
FMC1_HPC_PRSNT_M2C_B signal. Switch U26 adds an attached FMC to the JTAG chain as
determined by the FMC2_LPC_PRSNT_M2C_B signal.

Clock Generation

The ZC702 board provides three clock sources for the XC7Z020 AP SoC.
source devices for each clock.
Table 1-11: ZC702 Board Clock Sources
Clock Name
System Clock
User Clock
PS Clock
Table 1-12 lists the pin-to-pin connections from each clock source to the XC7Z020 AP SoC.
Table 1-12: Clock Connections, Source to XC7Z020 AP SoC
Clock Source Pin
U43.5
U43.4
U28.5
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Switch 1
Clock
Source
SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime). See
U43
System Clock.
Si570 3.3V LVDS I
U28
Labs). See Programmable User
SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency oscillator
U65
(SiTime). See Processing System Clock
Net Name XC7Z020 (U1) Pin
SYSCLK_N
SYSCLK_P
USRCLK_N
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DIP Switch SW10[1:2]
(1)
JTAG_SEL_1
0
1
0
1
Description
2
C programmable oscillator, 156.250 MHz default (Silicon
Clock.
Source.
C19
D18
Y8
Feature Descriptions
(1)
Switch 2 JTAG_SEL_2
0
0
1
1
Table 1-11 lists the
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