Xilinx ZCU106 User Manual page 39

The connections between the SPI flash memory and the XCZU7EV MPSoC are listed in
Table 3-6.
Table 3-6: Quad SPI Flash Memory Component Connections to MPSoC U1
XCZU7EV (U1) Pin
A25
C24
B24
E25
A24
D25
D26
C26
F26
B26
C27
B25
The configuration and Quad SPI flash memory section of the Zynq UltraScale+ MPSoC
Technical Reference Manual (UG1085)
more Quad SPI details, see the Micron MT25QU512ABB8ESF-0SIT data sheet at the Micron
website [Ref 15].
USB0 (MIO 52-63)
The USB interface on the PS-side serves multiple roles as a host or device controller. The
USB 3.0 interface is supported by the MPSoC GTR interface while the USB 2.0 capabilities of
the SMSC USB3320C controller are shared on a common USB 3.0 USB type A connector
(J96).
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
MIO4_QSPI_LWR_DQ0
MIO1_QSPI_LWR_DQ1
MIO2_QSPI_LWR_DQ2
MIO3_QSPI_LWR_DQ3
MIO0_QSPI_LWR_CLK
MIO5_QSPI_LWR_CS_B
MIO8_QSPI_UPR_DQ0
MIO9_QSPI_UPR_DQ1
MIO10_QSPI_UPR_DQ2
MIO11_QSPI_UPR_DQ3
MIO12_QSPI_UPR_CLK
MIO7_QSPI_UPR_CS_B
[Ref 2] provides details on using the memory. For
www.xilinx.com
Chapter 3: Board Component Descriptions
Quad-SPI U119 (LWR), U120 (UPR)
Pin # Pin Name
15
8
9 DQ2_WP_B
1 DQ3_RST_HOLD_B
16
7
15
8
9 DQ2_WP_B
1 DQ3_RST_HOLD_B
16
7
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DQ0
DQ1
C
S_B
DQ0
DQ1
C
S_B
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