Sfp/Sfp+ Connectors - Xilinx ZCU106 User Manual

Table 3-31: AES3 Audio Connections to MPSoC U1
XCZU7EV Schematic Net
(U1) Pin Name
G7 AES_IN
AE13 AES_OUT_P
AF13 AES_OUT_N
Notes:
1. Series resistor, inductor, and capacitor coupled.
2. Series resistor and inductor coupled.
3. Transformer coupled by T1 SC937-02LF.

SFP/SFP+ Connectors

[Figure 2-1, callout 18]
The ZCU106 board contains a small form-factor pluggable (SFP+) 1x2 dual-connector
(P1, P2) and cage assembly that accepts SFP or SFP+ modules.
SFP+ module connector circuitry implementation.
the dual connectors and the XCZU7EV MPSoC.
The SFPx_TX_DISABLE_TRANS default 2-pin jumper is On, which means the
Note:
SFPx_TX_DISABLE_TRANS net is pulled Low, enabling the TX output of the SFP module.
X-Ref Target - Figure 3-29
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
I/O Standard
LVCMOS33
(1) (3)
(2) (3)
Figure 3-29: Typical SFP Interface
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected Component
Pin Name
1 R
8
5
Figure 3-29
Table 3-32 lists the connections between
Device
U149
SN65HVD11DR
T1 SC937-02LF
shows a typical
X19193-050117
80
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