I2C1 (Mio 16-17) - Xilinx ZCU106 User Manual

Table 3-22: I2C0 U60 Address 0x75 MUX Target Bus Connections (Cont'd)
Reference
Designator
U49
U8
SYSMON_SDA/SCL (U60 Port 3) (level-shifted via U137)
U1

I2C1 (MIO 16-17)

The PS-side I2C1 interface provides access to I2C peripherals through a set of I2C switches.
The I2C1 PS-side connection is shared with the PL-side and the system controller.
Figure 3-18 shows a high-level view of the I2C1 bus connectivity represented in
and Table 3-24. TCA9548A U34 is set to 0x74 and TCA9548A U135 is set to 0x75.
X-Ref Target - Figure 3-18
U1
Bank 500
PS I2C1
MIO17/
MIO16
U1
Bank 65
PL I2C1
AL21/AH19
U41
MPS430
28 P4_1
29 P4_2
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Address
MAX15301 UTIL_3V3
0x1A
MAX15303 UTIL_5V0
0x1B
U1 BANK 28 B20/A22
0x32
U136
I2C1_SDA/SCL
L/S
U45
L/S
Figure 3-18: I2C1 Bus Topology
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Chapter 3: Board Component Descriptions
Device
U34
TCA9548A
IIC_EEPROM_SDA/SCL 0x34
SD0/SC0
SI5341_SDA/SCL
SD1/SC1
SDA/
USER_S1570_SDA/SCL 0x5D
SCL
SD2/SC2
USER_MGT_SI570_SDA/SCL 0x5D
SD3/SC3
S15328_SDA/SCL
SD4/SC4
0x74
U135
TCA9548A
FMC_HPC0_IIC_SDA/SCL
SD0/SC0
FMC_HPC1_IIC_SDA/SCL
SD1/SC1
SYSMON_SDA/SCL
SD2/SC2
DDR4_SODIMM_SDA/SCL
SDA/
SD3/SC3
Not Connected
SCL
SD4/SC4
Not Connected
SD5/SC5
SFP1_IIC_SDA/SCL
SD6/SC6
SFP0_IIC_SDA/SCL
SD7/SC7
0x75
Table 3-23
X19319-052417
65
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