Xilinx ZCU106 User Manual page 133

set_propertyPACKAGE_PIN AD12
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AH18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;
set_propertyPACKAGE_PIN AD15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM1"] ;
set_propertyPACKAGE_PIN AM16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM2"] ;
set_propertyPACKAGE_PIN AP18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM3"] ;
set_propertyPACKAGE_PIN AE18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM4"] ;
set_propertyPACKAGE_PIN AH22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM5"] ;
set_propertyPACKAGE_PIN AL20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM6"] ;
set_propertyPACKAGE_PIN AP19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM7"] ;
set_propertyPACKAGE_PIN AF16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"] ;
set_propertyPACKAGE_PIN AF18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"] ;
set_propertyPACKAGE_PIN AG15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"] ;
set_propertyPACKAGE_PIN AF17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"] ;
set_propertyPACKAGE_PIN AF15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"] ;
set_propertyPACKAGE_PIN AG18
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"] ;
set_propertyPACKAGE_PIN AG14
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"] ;
set_propertyPACKAGE_PIN AE17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"] ;
set_propertyPACKAGE_PIN AA14
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"] ;
set_propertyPACKAGE_PIN AC16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"] ;
set_propertyPACKAGE_PIN AB15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"] ;
set_propertyPACKAGE_PIN AD16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"] ;
set_propertyPACKAGE_PIN AB16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"] ;
set_propertyPACKAGE_PIN AC17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"] ;
set_propertyPACKAGE_PIN AB14
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"] ;
set_propertyPACKAGE_PIN AD17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"] ;
set_propertyPACKAGE_PIN AJ16
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ16"] ;
set_propertyPACKAGE_PIN AJ17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ17"] ;
set_propertyPACKAGE_PIN AL15
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ18"] ;
set_propertyPACKAGE_PIN AK17
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ19"] ;
set_propertyPACKAGE_PIN AJ15
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Appendix B: Master Constraints File Listing
[get_ports "DDR4_CS_B"] ;
[get_ports "DDR4_CS_B"] ;
[get_ports "DDR4_DM0"] ;
[get_ports "DDR4_DM1"] ;
[get_ports "DDR4_DM2"] ;
[get_ports "DDR4_DM3"] ;
[get_ports "DDR4_DM4"] ;
[get_ports "DDR4_DM5"] ;
[get_ports "DDR4_DM6"] ;
[get_ports "DDR4_DM7"] ;
[get_ports "DDR4_DQ0"] ;
[get_ports "DDR4_DQ1"] ;
[get_ports "DDR4_DQ2"] ;
[get_ports "DDR4_DQ3"] ;
[get_ports "DDR4_DQ4"] ;
[get_ports "DDR4_DQ5"] ;
[get_ports "DDR4_DQ6"] ;
[get_ports "DDR4_DQ7"] ;
[get_ports "DDR4_DQ8"] ;
[get_ports "DDR4_DQ9"] ;
[get_ports "DDR4_DQ10"] ;
[get_ports "DDR4_DQ11"] ;
[get_ports "DDR4_DQ12"] ;
[get_ports "DDR4_DQ13"] ;
[get_ports "DDR4_DQ14"] ;
[get_ports "DDR4_DQ15"] ;
[get_ports "DDR4_DQ16"] ;
[get_ports "DDR4_DQ17"] ;
[get_ports "DDR4_DQ18"] ;
[get_ports "DDR4_DQ19"] ;
[get_ports "DDR4_DQ20"] ;
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