Fmc Hpc1 Connector J4 - Xilinx ZCU106 User Manual

FMC HPC1 Connector J4

[Figure 2-1, callout 33]
The FMC connector at J4 (HPC1) implements a subset of the full FMC HPC connectivity:
• 34 single-ended, or 17 differential user-defined pairs (LA[00:16])
• One GTH transceiver DP differential pair
• One GBTCLK differential clocks
• 159 ground and 15 power connections
The ZCU106 board FMC VADJ voltage VADJ_FMC_BUS for the J5 (HPC0) and J4 (HPC1) FMC
connectors is determined by the MAX15301 U63 voltage regulator described in
Power System, page
HPC1 J4 connections to XCZU7EV U1 are shown in
Table 3-48: J4 HPC1 FMC Section A and B Connections to XCZU7EV U1
J4 Pin Schematic Net Name
A2
A3
A6
A7
A10
A11
A14
A15
A18
A19
A22
A23
A26
A27
A30
A31
A34
A35
A38
A39
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
122. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The
I/O
U1 Pin
Standard
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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Chapter 3: Board Component Descriptions
Table 3-48 through
J4 Pin Schematic Net Name
B1 NC
B4 NC
B5 NC
B8 NC
B9 NC
B12 NC
B13 NC
B16 NC
B17 NC
B20 NC
B21 NC
B24 NC
B25 NC
B28 NC
B29 NC
B32 NC
B33 NC
B36 NC
B37 NC
B40 NC
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Board
Table 3-52.
I/O
U1 Pin
Standard
110