Xilinx ZCU106 User Manual page 99

Table 3-41: GTH Transceiver Bank 227 Interface Connections
XCZU7EV XCZU7EV Pin
(U1) Pin Name
M4 MGTHTXP0
M3 MGTHTXN0
N2 MGTHRXP0
N1 MGTHRXN0
L6 MGTHTXP1
L5 MGTHTXN1
L2 MGTHRXP1
L1 MGTHRXN1
K4 MGTHTXP2
K3 MGTHTXN2
J2 MGTHRXP2
J1 MGTHRXN2
H4 MGTHTXP3
H3 MGTHTXN3
G2 MGTHRXP3
G1 MGTHRXN3
T8 MGTREFCLK0P
T7 MGTREFCLK0N
R10 MGTREFCLK1P
R9 MGTREFCLK1N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Schematic Net Name
FMC_HPC0_DP6_C2M_P
FMC_HPC0_DP6_C2M_N
FMC_HPC0_DP6_M2C_P
FMC_HPC0_DP6_M2C_N
FMC_HPC0_DP5_C2M_P
FMC_HPC0_DP5_C2M_N
FMC_HPC0_DP5_M2C_P
FMC_HPC0_DP5_M2C_N
FMC_HPC0_DP7_C2M_P
FMC_HPC0_DP7_C2M_N
FMC_HPC0_DP7_M2C_P
FMC_HPC0_DP7_M2C_N
FMC_HPC0_DP4_C2M_P
FMC_HPC0_DP4_C2M_N
FMC_HPC0_DP4_M2C_P
FMC_HPC0_DP4_M2C_N
FMC_HPC0_GBTCLK1_M2C_C_P
FMC_HPC0_GBTCLK1_M2C_C_N
USER_MGT_SI570_CLOCK2_C_P
USER_MGT_SI570_CLOCK2_C_N
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Chapter 3: Board Component Descriptions
(2)
Pin No.
B36
B37 DP6_C2M_N
B16
B17 DP6_M2C_N
A38
A39 DP5_C2M_N
A18
A19 DP5_M2C_N
B32
B33 DP7_C2M_N
B12
B13 DP7_M2C_N
A34
A35 DP4_C2M_N
A14
A15 DP4_M2C_N
(1)
B20 GBTCLK1_M2C_P
(1)
B21 GBTCLK1_M2C_N
(1)
13
(1)
14
Connected To
Pin Name Device
DP6_C2M_P
DP6_M2C_P
DP5_C2M_P
DP5_M2C_P
DP7_C2M_P
FMC HPC0 J5
DP7_M2C_P
DP4_C2M_P
DP4_M2C_P
Q2_P
SI53340 U51
1-to-2 buffer
Q2_N
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