Xilinx ZCU106 User Manual page 135

set_propertyPACKAGE_PIN AL23
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ50"] ;
set_propertyPACKAGE_PIN AJ21
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ51"] ;
set_propertyPACKAGE_PIN AK20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ52"] ;
set_propertyPACKAGE_PIN AJ19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ53"] ;
set_propertyPACKAGE_PIN AK19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ54"] ;
set_propertyPACKAGE_PIN AJ20
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ55"] ;
set_propertyPACKAGE_PIN AP22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ56"] ;
set_propertyPACKAGE_PIN AN22
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ57"] ;
set_propertyPACKAGE_PIN AP21
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ58"] ;
set_propertyPACKAGE_PIN AP23
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ59"] ;
set_propertyPACKAGE_PIN AM19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ60"] ;
set_propertyPACKAGE_PIN AM23
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ61"] ;
set_propertyPACKAGE_PIN AN19
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ62"] ;
set_propertyPACKAGE_PIN AN23
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ63"] ;
set_propertyPACKAGE_PIN AJ14
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS0_C"] ;
set_propertyPACKAGE_PIN AH14
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS0_T"] ;
set_propertyPACKAGE_PIN AA15
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS1_C"] ;
set_propertyPACKAGE_PIN AA16
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS1_T"] ;
set_propertyPACKAGE_PIN AK14
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS2_C"] ;
set_propertyPACKAGE_PIN AK15
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS2_T"] ;
set_propertyPACKAGE_PIN AN14
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS3_C"] ;
set_propertyPACKAGE_PIN AM14
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS3_T"] ;
set_propertyPACKAGE_PIN AB18
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS4_C"] ;
set_propertyPACKAGE_PIN AA18
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS4_T"] ;
set_propertyPACKAGE_PIN AG23
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS5_C"] ;
set_propertyPACKAGE_PIN AF23
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS5_T"] ;
set_propertyPACKAGE_PIN AK23
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS6_C"] ;
set_propertyPACKAGE_PIN AK22
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS6_T"] ;
set_propertyPACKAGE_PIN AN21
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS7_C"] ;
set_propertyPACKAGE_PIN AM21
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Appendix B: Master Constraints File Listing
[get_ports "DDR4_DQ50"] ;
[get_ports "DDR4_DQ51"] ;
[get_ports "DDR4_DQ52"] ;
[get_ports "DDR4_DQ53"] ;
[get_ports "DDR4_DQ54"] ;
[get_ports "DDR4_DQ55"] ;
[get_ports "DDR4_DQ56"] ;
[get_ports "DDR4_DQ57"] ;
[get_ports "DDR4_DQ58"] ;
[get_ports "DDR4_DQ59"] ;
[get_ports "DDR4_DQ60"] ;
[get_ports "DDR4_DQ61"] ;
[get_ports "DDR4_DQ62"] ;
[get_ports "DDR4_DQ63"] ;
[get_ports "DDR4_DQS0_C"] ;
[get_ports "DDR4_DQS0_T"] ;
[get_ports "DDR4_DQS1_C"] ;
[get_ports "DDR4_DQS1_T"] ;
[get_ports "DDR4_DQS2_C"] ;
[get_ports "DDR4_DQS2_T"] ;
[get_ports "DDR4_DQS3_C"] ;
[get_ports "DDR4_DQS3_T"] ;
[get_ports "DDR4_DQS4_C"] ;
[get_ports "DDR4_DQS4_T"] ;
[get_ports "DDR4_DQS5_C"] ;
[get_ports "DDR4_DQS5_T"] ;
[get_ports "DDR4_DQS6_C"] ;
[get_ports "DDR4_DQS6_T"] ;
[get_ports "DDR4_DQS7_C"] ;
[get_ports "DDR4_DQS7_T"] ;
www.xilinx.com
135
Send Feedback