Revision History The following table shows the revision history for this document. Date Version Revision 03/28/2018 Initial Xilinx release. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Chapter 1 Introduction Overview The ZCU106 is a general purpose evaluation board for rapid-prototyping based on the ® ™ ZU7EV silicon part and package in the 16 nm FinFET Zynq UltraScale+ MPSoC. The ® ™ ZU7EV device integrates a quad core ARM...
Chapter 1: Introduction Board Features The ZCU106 evaluation board features are listed here. Detailed information for each feature is provided in Component Descriptions in Chapter • XCZU7EV-2, FFVC1156 package • PL V for range in data sheet CCINT • Form factor for PCIe® Gen[1-3]x4 endpoint (PL GTH transceiver), Micro-ATX chassis footprint •...
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Operational status LEDs (power status, INIT, DONE, PG, JTAG status, DDR power good) • Power management The ZCU106 provides designers a rapid prototyping platform using the XCZU7EV-2FFVC1156 device. The ZU7EV contains many PS hard block peripherals exposed through the multi-use I/O (MIO) interface and several FPGA programmable logic (PL), high-density (HD), and high-performance (HP) banks.
Length: 9.5 inch (24.13 cm) Thickness: 0.062 inch ±0.005 inch (0.157 cm ±0.0127 cm) A 3D model of this board is not available. Note: The ZCU106 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI IMPORTANT: ® Express card.
Chapter 1: Introduction Environmental Temperature Operating: 0°C to +45°C Storage: -25°C to +60°C Humidity 10% to 90% non-condensing Operating Voltage +12 V ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Always refer to the schematic, layout, and XDC files of the specific ZCU106 version of interest for such details. The ZCU106 board can be damaged by electrostatic discharge (ESD). Follow standard ESD CAUTION! prevention measures when handling the board.
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Round callout references a component Square callout references a component on the front side of the board on the back side of the board X19001-022218 Figure 2-1: ZCU106 Evaluation Board Components ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Chapter 2: Board Setup and Configuration Default Jumper and Switch Settings Figure 2-2 shows the ZCU106 board jumper header and DIP switch locations. Each numbered component shown in the figure is keyed to Table 2-2 Table 2-3 (for default switch settings). Both tables reference the respective schematic (0381770) page numbers.
3: SW2 toward the label ON is a 0. 1 through 5 are tied to MSP430 U41 GPIO[1:5]. 4: SW3 5: SW4 SW13 GPIO All Off Main power switch ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Figure 2-3. a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J52 on the ZCU106 board. b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.
J52. The ATX 6-pin connector has a different pin out than J52. Connecting an ATX 6-pin connector into J52 damages the ZCU106 evaluation board and voids the board warranty. 8. Slide the ZCU106 board power switch SW1 to the ON position. The PC can now be powered on.
3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in Figure 2-1. See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for more information about Zynq UltraScale+ MPSoC configuration options. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Cortex -A53 64-bit quad-core processor and Cortex-R5 dual-core real-time processor. Production ZCU106 evaluation boards will ship with -2 speed grade devices. Support of multiple speed grades requires voltage adjustments. The V supplies are user adjustable via the PMBus with the voltage ranges listed in...
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0.876 For -1LI and -2LE (V = 0.72V) devices: CCINT 0.698 0.720 0.742 CCINT PL internal supply voltage. For -3E devices: PL internal supply voltage. 0.873 0.900 0.927 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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AES-GCM Processor System PCIe DDRC (DDR4/3/3L, LPDDR3/4) 128 KB RAM To ACP Gen4 32-bit/64-bit Battery Low Power Full Power Power 64-bit 128-bit X16387-050517 Figure 3-1: Top-Level Block Diagram ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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For additional information on Zynq UltraScale+ MPSoC devices, see the Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891) [Ref 1]. See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for more information about Zynq UltraScale+ MPSoC configuration options. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Chapter 3: Board Component Descriptions Encryption Key Battery Backup Circuit The XCZU7EV MPSoC U1 implements bit stream encryption key technology. The ZCU106 board provides the encryption key backup battery circuit shown in Figure 3-2. X-Ref Target - Figure 3-2 To MPSoC U1 Pin Y23...
Chapter 3: Board Component Descriptions I/O Voltage Rails The XCZU7EV MPSoC PL I/O bank voltages on the ZCU106 board are listed in Figure 3-2. Table 3-2: I/O Voltage Rails XCZU7EV Power Net Name Voltage Connected To PL Bank 28 1.8V...
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Chapter 3: Board Component Descriptions The ZCU106 supports full power-off suspend mode where only the system controller and the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a self-refresh state and has its reset input controlled by the system controller such that the memory is not reset when waking-up from suspend mode.
CS0_N AK32 DDR4_SODIMM_CS1_B CS1_N The ZCU106 DDR4 SODIMM interface adheres to the constraints guidelines documented in the “PCB Guidelines for DDR4” section of the UltraScale Architecture PCB Design Guide (UG583) [Ref 3]. The DDR4 SODIMM interface is a 40Ω impedance implementation. Other...
DDR4_CS_B SSTL12_DCI CS_B U2,U99-U101 The ZCU106 board DDR4 64-bit component memory interface adheres to the constraints guidelines documented in the “PCB Guidelines for DDR4” section of UltraScale Architecture PCB Design User Guide (UG583)[Ref 3]. The ZCU106 DDR4 component interface is a 40Ω...
• Part number: MT25QU512ABB8ESF-0SIT (Micron) • Supply voltage: 1.8V • Datapath width: 8 bits • Data rate: various depending on single, dual, or quad mode ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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USB 3.0 interface is supported by the MPSoC GTR interface while the USB 2.0 capabilities of the SMSC USB3320C controller are shared on a common USB 3.0 USB type A connector (J96). ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
Figure 3-3). A USB cable 3.0 A to A is supplied in the ZCU106 evaluation kit (host computer USB 3.0 A port to ZCU106 board connector J96). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device, which drives the physical USB bus.
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2-3 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C887 and jumping pins 1-2 on header J112. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
This interface is used for the SD boot mode and supports SD3.0 access post boot. SD Card Interface [Figure 2-1, callout 6] The ZCU106 board includes a secure digital input/output (SDIO) interface to provide access to general purpose non-volatile SDIO memory cards and peripherals. See the SanDisk Corporation [Ref 17]...
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Chapter 3: Board Component Descriptions Figure 3-5 shows the connections of the SD card interface on the ZCU106 board. X-Ref Target - Figure 3-5 X19005-050117 Figure 3-5: SD Card Interface The NXP SD3.0 level shifter is mounted on an Aries adapter board that has the pin mapping...
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Net Name (U1) Pin Pin # Pin Name MIO39_SDIO_SEL MIO40_SDIO_DIR_CMD DIR_CMD MIO41_SDIO_DIR_DAT0 DIR_0 MIO42_SDIO_DIR_DAT1_3 DIR_1_3 MIO46_SDIO_DAT0 DATA0_H MIO47_SDIO_DAT1 DATA1_H MIO48_SDIO_DAT2 DATA2_H MIO49_SDIO_DAT3 DATA3_H MIO50_SDIO_CMD CMD_H MIO51_SDIO_CLK CLK_IN MIO44_SDIO_PROTECT MIO45_SDIO_DETECT ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
J2 USB micro AB connector connected to U152 FTDI USB JTAG bridge • J8 2x7 2 mm shrouded, keyed JTAG pod flat cable connector • J6 2x10 ARM JTAG male pin header The ZCU106 board JTAG chain is shown in Figure 3-6. X-Ref Target - Figure 3-6 JTAG...
JTAG chain connects to the U1 XCZU7EV MPSoC. EMIO ARM Trace Port [Figure 2-1, callout 34] The ZCU106 evaluation board provides a trace/debug 38-pin Mictor connector, P6. Figure 3-7 shows connector P6 with its MPSoC bank 87/88 connections. X-Ref Target - Figure 3-7...
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TRACETRST_B LVCMOS33 TRACESRST_B LVCMOS33 For more information about managing the Zynq MPSoC extended MIO (EMIO) trace port connections, see the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Chapter 3: Board Component Descriptions Clock Generation The ZCU106 board provides fixed and variable clock sources for the XCZU7EV MPSoC. Table 3-12 lists the source devices for each clock. Table 3-12: Clock Sources Clock (Net) Name Frequency Clock Source Fixed Frequency Clocks PS_REF_CLK 33.33 MHz...
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J80.1 USER_SMA_MGT_CLOCK_N U108.28 HDMI_SI5324_OUT_P U108.29 HDMI_SI5324_OUT_N U20.28 SFP_SI5328_OUT_P U20.29 SFP_SI5328_OUT_N Notes: 1. U1 XCU7EV Bank 503 supports LVCMOS level inputs. 2. U1 MGT (I/O standards do not apply). ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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The SI5341B (U69) is a one-time programmable clock source. For more details, see the SI5341B data sheet [Ref 19]. The clock circuit is shown in Figure 3-8. X-Ref Target - Figure 3-8 X19007-050117 Figure 3-8: SI5341B Clock Generator ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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On power up, the user clock defaults to an output frequency of 300.000 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the ZCU106 board reverts this user clock to the default frequency of 300.000 MHz.
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10 MHz to 810 MHz through an I2C interface. Power cycling the ZCU106 board reverts this user clock to the default frequency of 156.250 MHz. This oscillator can be reprogrammed from MSP430 system controller U41 (see...
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[Figure 2-1, callout 48] The ZCU106 board provides a pair of SMAs for differential AC coupled user MGT clock input into FPGA U1 MGTH bank 224. This differential signal pair is series-capacitor coupled. The P-side SMA J79 signal USER_SMA_MGT_CLOCK_P is connected to U1 MGTREFCLK1P pin AA10.
SW9 pushbutton (U59.6), the MAX16025 U22 MPSoC PS-side POR reset device (U59.1), or the I2C0 connected U97 TCA6416A I/O expander port P06 pin 10 (U59.3). X-Ref Target - Figure 3-13 X19174-052417 Figure 3-13: Ethernet PHY Reset Circuit ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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MDIO/MDC. LED_2 is assigned to the activity indicator (ACT) and LED_0 indicates link established. For more Ethernet PHY details, see the TI DS83867 data sheet [Ref 20]. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
CP2108 USB UART Interface [Figure 2-1, callout 13] The CP2108 quad USB-UART on the ZCU106 board provides four level-shifted UART connections through single micro-B USB connector J83. Channel 0 and 1 are PS-side MIO connections described in the UART0 (MIO 18-19) section.
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Table 3-16: XCZU7EV U1 to CP2108 U40 Connections via L/S U52 CP2108 U40 XCZU7EV (U1) Net Name Pin Name Pin # AH17 UART2_TXD_O_FPGA_RXD TX_2 AL17 UART2_RXD_I_FPGA_TXD RX_2 AM15 UART2_RTS_O_B RTS_2 AP17 UART2_RTS_I_B CTS_2 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Table 3-17: MSP430 U41 to CP2108 U40 Connections via L/S U53 MSP430 U41 CP2108 U40 Net Name Pin Name Pin # Pin Name Pin # P3_3 UART3_TXD_O_MSP430_UCA0_RXD TX_3 P3_3 UART3_RXD_I_MSP430_UCA0_TXD RX_3 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
TCA6416A U97 connections. The devices on each bus of the I2C0 multiplexer U60 are identified in Table 3-21 and the multiplexer bus connections are listed in Table 3-22. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Note: See the User I2C0 Receptacle PCA9544A section for more details on J160. PS_PMBUS_SDA/SCL SDA/ SD0/SC0 PL_PMBUS_SDA/SCL SD1/SC1 MAXIM_PMBUS_SDA/SCL SD2/SC2 SYSMON_SDA/SCL SD3/SC3 0x75 X19176-083017 Figure 3-17: I2C0 Bus Topology ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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The PS_PMBUS and PL_PMBUS INA226 power monitor device I2C addresses are listed in Note: Table 3-22. The MAXIM_PMBUS power system device I2C addresses are listed in Table 3-22 Table 3-54. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
TI SN65HVD232 CAN-bus transceiver U122 to the 0.1 inch pitch 8-pin male header J98 (see Figure 3-20 Figure 3-21). X-Ref Target - Figure 3-20 CAN_TX CANH TXS0104E SN65HVD232 CANL CAN_RX X16533-050117 Figure 3-20: PS-Side CAN Bus Interface Diagram ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
[Figure 2-1, callout 14] The ZCU106 board provides an HDMI® video output using a TI SN65DP159RGZ re-timer at U94. The output is provided on a TE Connectivity 1888811-1 right-angle dual-stacked HDMI type-A receptacle at P7. The SN65DP159RGZ device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) re-timer supporting digital video interface (DVI) 1.0, HDMI 1.4b, and 2.0 output signals.
[Figure 2-1, callout 41] The ZCU106 board includes a Silicon Labs Si5319C jitter attenuator U108 (2 kHz – 945 MHz). The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 67 (HDMI_REC_CLOCK_C_P, pin G14 and HDMI_REC_CLOCK_C_N, pin F13) for jitter attenuation.
12 Gb/s [nominal] component digital signals or packetized data along with the mapping of various source image formats to the bit-serial data structure. The SDI video circuit is shown Figure 3-27. X-Ref Target - Figure 3-27 X19191-050117 Figure 3-27: SDI Video ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. 3. Level-shifted V to PS_DDR4_VPP_2V5 (1.8V-to-2.5V) at U146 SN74AVC8T245. ADJ_FMC 4. Level-shifted V to PS_DDR4_VPP_2V5 (1.8V-to-2.5V) at U145 SN74AVC4T245. ADJ_FMC ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Ref_2_IEC_60958-1_2ndEd_2004-03. The AES3 audio circuit is shown in Figure 3-28 and the connections are listed in Table 3-31. X-Ref Target - Figure 3-28 X19192-050117 Figure 3-28: AES Audio ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
[Figure 2-1, callout 11] The ZCU106 board includes a Silicon Labs Si5328B jitter attenuator U20 (8 kHz – 808 MHz). The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 68 (SFP_REC_CLOCK_C_P, pin H11 and SFP_REC_CLOCK_C_N, pin G11) for jitter attenuation. The...
User PMOD GPIO Headers [Figure 2-1, callout 20, 21] The ZCU106 evaluation board supports two PMOD GPIO headers J55 (right-angle female) and J87 (vertical male). The 3.3V PMOD nets are level-shifted and wired to the XCZU7EV device U1 banks 28, 66, and 68.
LVCMOS18 User I2C0 Receptacle [Figure 2-1, callout 21] The ZCU106 evaluation board supports a PMOD 2X6 receptacle (right-angle female) J160. Figure 3-33 shows the I2C0 PMOD receptacle J160. The I2C0 nets are a branch of the I2C0 main bus (see...
Chapter 3: Board Component Descriptions User I/O [Figure 2-1, callouts 22-25] The ZCU106 board provides these user and general purpose I/Os: • Eight user LEDs (callout 22) GPIO_LED[7-0]: DS38, DS37, DS39, DS40, DS41, DS42, DS43, DS44 ° • Five user pushbuttons and CPU reset switch (callouts 24 and 25) GPIO_SW_[NESWC]: SW18, SW17, SW16, SW14, SW15 °...
VCCPSPLL 1.2 VDC power on DS16 VCCPSINTLP_PGOOD Green VCCPSINTLP 0.85 VDC power on DS17 DDR4_DIMM_VDDQ_PGOOD Green DDR4_DIMM_VDDQ 1.2 VDC power on DS18 MGTRAVTT_PGOOD Green MGTRAVTT 1.81 VDC power on ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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PS USB 3.0 ULPI VBUS power error Notes: 1. See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for more information about Zynq UltraScale+ MPSoC configuration pins. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
The GTH transceivers in the XCZU7EV device are grouped into four channels referred to as Quads. The reference clock for a Quad can be sourced from the Quad above or the Quad below the GTH Quad of interest. There are five GTH Quads on the ZCU106 board with connectivity as listed here: Quad 223: •...
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MGTREFCLK1 - USER_MGT_SI570_CLOCK1_C_P/N • Contains four GTH transceivers allocated to FMC_HPC0_DP[0:3]_C2M/M2C_P/N Quad 227: • MGTREFCLK0 - FMC_HPC0_GBTCLK1_M2C_C_P/N • MGTREFCLK1 - USER_MGT_SI570_CLOCK2_C_P/N • Contains four GTH transceivers allocated to FMC_HPC0_DP[4:7]_C2M/M2C_P/N ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Chapter 3: Board Component Descriptions GTH transceiver interface assignments on the ZCU106 are shown in Figure 3-38. X-Ref Target - Figure 3-38 X19198-050117 Figure 3-38: GTH Transceiver Bank Assignments ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
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Si5328. SFP+ modules typically provide an I2C based control interface. This I2C interface is accessible for each individual SFP+ module through the I2C multiplexer topology on the ZCU106. HDMI Three PL-side GTH transceivers are dedicated for HDMI source and sink. Modes supported are 4K, 2K at 60 f/s, and 2160p60.
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MGTHRXP3 FMC_HPC1_DP0_M2C_P DP0_M2C_P MGTHRXN3 FMC_HPC1_DP0_M2C_N DP0_M2C_N MGTREFCLK0P HDMI_SI5324_OUT_C_P CKOUT1_P SI5319C JITTER ATTEN. U108 MGTREFCLK0N HDMI_SI5324_OUT_C_N CKOUT1_N Notes: 1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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PETn0 MGTREFCLK0P PCIE_CLK_P REFCLK+ MGTREFCLK0N PCIE_CLK_N REFCLK- AA10 MGTREFCLK1P USER_SMA_MGT_CLOCK_C_P SMA J79 MGTREFCLK1N USER_SMA_MGT_CLOCK_C_N SMA J80 Notes: 1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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FMC_HPC1_GBTCLK0_M2C_C_P GBTCLK0_M2C_P FMC HPC1 J4 MGTREFCLK0N FMC_HPC1_GBTCLK0_M2C_C_N GBTCLK0_M2C_N MGTREFCLK1P SFP_SI5328_OUT_C_P CKOUT1_P SI5328B U20 MGTREFCLK1N SFP_SI5328_OUT_C_N CKOUT1_N Notes: 1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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MGTREFCLK0P FMC_HPC0_GBTCLK0_M2C_C_P GBTCLK0_M2C_P MGTREFCLK0N FMC_HPC0_GBTCLK0_M2C_C_N GBTCLK0_M2C_N MGTREFCLK1P USER_MGT_SI570_CLOCK1_C_P Q1_P SI53340 U51 1-to-2 buffer MGTREFCLK1N USER_MGT_SI570_CLOCK1_C_N Q1_N Notes: 1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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MGTREFCLK0P FMC_HPC0_GBTCLK1_M2C_C_P GBTCLK1_M2C_P MGTREFCLK0N FMC_HPC0_GBTCLK1_M2C_C_N GBTCLK1_M2C_N MGTREFCLK1P USER_MGT_SI570_CLOCK2_C_P Q2_P SI53340 U51 1-to-2 buffer MGTREFCLK1N USER_MGT_SI570_CLOCK2_C_N Q2_N Notes: 1. Series capacitor coupled. 2. MGT connections I/O standard not applicable. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
The PS GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0) and SATA, as shown in Figure 3-41. X-Ref Target - Figure 3-41 X19201-050117 Figure 3-41: PS-GTR Lane Assignments ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
2. MGT connections I/O standard not applicable. FPGA Mezzanine Card Interface [Figure 2-1, callouts 32, 33] The ZCU106 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC) specification [Ref 23] by providing subset implementations of high pin count connectors at J5 (HPC0) and J4 (HPC1).
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Chapter 3: Board Component Descriptions The ZCU106 board FMC VADJ voltage VADJ_FMC_BUS for the J5 (HPC0) and J4 (HPC1) FMC connectors is determined by the MAX15301 U63 voltage regulator described in Board Power System, page 122. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The...
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5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13. 6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal. 7. U1 MGT (I/O standards do not apply). ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
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Table 3-45: J5 HPC0 FMC Section E and F Connections to XCZU7EV U1 Schematic Net Name Schematic Net Name Standard Standard P/U to 3.3V FMC_HPC0_PG_M2C via R277 VADJ_FMC_BUS VADJ_FMC_BUS ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13. 6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal. 7. U1 MGT (I/O standards do not apply). ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
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Chapter 3: Board Component Descriptions Table 3-47: J5 HPC0 FMC Section J and K Connections to XCZU7EV U1 J5 Pin Schematic Net Name Schematic Net Name Standard U1 Pin Standard ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
One GBTCLK differential clocks • 159 ground and 15 power connections The ZCU106 board FMC VADJ voltage VADJ_FMC_BUS for the J5 (HPC0) and J4 (HPC1) FMC connectors is determined by the MAX15301 U63 voltage regulator described in Board Power System, page 122.
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4. J4 HPC1 TDO-TDI connections to U24 HPC1 FMC JTAG bypass switch (N.C. normally-closed/bypassing J4 until an FMC card is plugged onto J4). 5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal. 6. U1 MGT (I/O standards do not apply). ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Table 3-50: J4 HPC1 FMC Section E and F Connections to XCZU7EV U1 J4 Pin Schematic Net Name U1 Pin J4 Pin Schematic Net Name U1 Pin Standard Standard FMC_HPC1_PG_M2C P/U to 3.3V via R250 VADJ_FMC_BUS VADJ_FMC_BUS ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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LVDS FMC_HPC1_LA15_P LVDS FMC_HPC1_LA15_N LVDS VADJ_FMC_BUS VADJ_FMC_BUS Notes: 1. FMC_HPC1_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U24.4 OE control signal is driven from I2C I/O expander U97.14. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Table 3-52: J4 HPC1 FMC Section J and K Connections to XCZU7EV U1 J4 Pin Schematic Net Name U1 Pin J4 Pin Schematic Net Name U1 Pin Standard Standard ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Figure 3-43. The ZCU106 uses the Maxim MAX6643 fan controller, which autonomously controls the fan speed by controlling the pulse width modulation (PWM) signal to the fan based on the die temperature sensed via the FPGA's DXP and DXN pins. The fan rotates slowly (acoustically quiet) when the FPGA is cool and rotates faster as the FPGA heats up (acoustically noisy).
A host PC resident system controller user interface (SCUI) is provided on the ZCU106 web page. This GUI enables you to query and control select programmable features such as clocks, FMC functionality, and power system parameters.
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1. Ensure that the Silicon Labs VCP USB-UART drivers are installed (see [Ref 7]). 2. Download the SCUI host PC application. 3. Connect the micro-USB to ZCU106 USB-UART connector (J83). 4. Power-cycle the ZCU106. 5. Observe that SYSCTLR LED0 (DS47) blinks and LED1 DS46 is illuminated. 6. Launch the SCUI.
ZCU106 Reserved Reserved Switches [Figure 2-1, callouts 27, 29, 31, and 46] The ZCU106 board includes power, configuration, and reset switches: • SW1 power on/off slide switch (callout 29) • SW5 (PS_PROG_B), active-Low pushbutton (callout 31) • SW3 (SRST_B), active-Low pushbutton (callout 27) •...
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[Figure 2-1, callout 29] The ZCU106 board power switch is SW1. Sliding the switch actuator from the off to the on position applies 12V power from J52, a 6-pin mini-fit connector. Green LED DS2 illuminates when the ZCU106 board power is on. See...
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PS software. See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for information about Zynq UltraScale+ MPSoC configuration. X-Ref Target - Figure 3-46 X16549-052417 Figure 3-46: PS_PROG_B Pushbutton Switch SW5 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal. When the voltage at IN1 is below its threshold or EN1 (P.B. switch SW4 is pressed) goes Low, OUT1 (PS_POR_B) goes Low. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
Board Power System [Figure 2-1, callout 35] The ZCU106 hosts a Maxim PMBus based power system. Each individual Maxim MAX20751EKX, MAX15301, or MAX15303 voltage regulator has a PMBus interface. Figure 3-48 shows the ZCU106 power system block diagram. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
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Chapter 3: Board Component Descriptions X-Ref Target - Figure 3-48 X19206-022218 Figure 3-48: Power System Block Diagram ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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Chapter 3: Board Component Descriptions The ZCU106 evaluation board uses power regulators and PMBus compliant POL controllers from Maxim Integrated Circuits [Ref 22] to supply the core and auxiliary voltages listed in Table 3-54. The schematic page references are to 0381770.
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PMBus programming for the Maxim InTune power controllers is available at the Maxim website [Ref 22]. The PCB layout and power system design meets the recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583) [Ref ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
PMBus is accessible by the system controller, which can also display the rail voltage measurement made by its sourcing Maxim controller. User IP in the MPSoC PL can access the same set of PMBus resident devices through the logic I2C0 connections. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
Figure A-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) J2 defined by the VITA 57.1 FMC specification. For a description of how the ZCU106 evaluation board implements the FMC specification, see FPGA Mezzanine Card Interface, page...
Master Constraints File Listing Overview The master Xilinx design constraints (XDC) file template for the ZCU106 board provides for designs targeting the ZCU106 evaluation board. Net names in the constraints listed correlate with net names on the latest ZCU106 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.
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#Other net PACKAGE_PIN AG31 - DR4_SODIMM_A10 Bank 504 - PS_DDR_A10 #Other net PACKAGE_PIN AF31 - DR4_SODIMM_A11 Bank 504 - PS_DDR_A11 #Other net PACKAGE_PIN AG30 - DR4_SODIMM_A12 Bank 504 - PS_DDR_A12 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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#Other net PACKAGE_PIN AH27 - DR4_SODIMM_DQ25 Bank 504 - PS_DDR_DQ25 #Other net PACKAGE_PIN AJ27 - DR4_SODIMM_DQ26 Bank 504 - PS_DDR_DQ26 #Other net PACKAGE_PIN AK27 - DR4_SODIMM_DQ27 Bank 504 - PS_DDR_DQ27 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
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#Other net PACKAGE_PIN AB34 - DR4_SODIMM_DQS6_C Bank 504 - PS_DDR_DQS_N6 #Other net PACKAGE_PIN AB33 - DR4_SODIMM_DQS6_T Bank 504 - PS_DDR_DQS_P6 #Other net PACKAGE_PIN W32 - DR4_SODIMM_DQS7_C Bank 504 - PS_DDR_DQS_N7 ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Methods of Measurement This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018...
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. ZCU106 Board User Guide Send Feedback UG1244 (v1.0) March 28, 2018 www.xilinx.com...
Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.
Appendix D: Additional Resources and Legal Notices References The most up to date information related to the ZCU106 board and its documentation is available on the ZCU106 Evaluation Kit website. These Xilinx documents provide supplemental material useful with this guide: 1.
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
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