Xilinx ZCU106 User Manual page 95

SMA
One MGT in bank 225 is provided on TX and RX SMA connector pairs. Available MGT clocks
include the FMC defined GBT clock 0 for HPC1 and a jitter attenuated recovered clock from
a Si5328. Table 3-37
connections.
Table 3-37: GTH Transceiver Bank 223 Interface Connections
XCZU7EV XCZU7EV Pin
(U1) Pin Name
AN6 MGTHTXP0
AN5 MGTHTXN0
AM4 MGTHTXP1
AM3 MGTHTXN1
AL6 MGTHTXP2
AL5 MGTHTXN2
AP4 MGTHRXP0
AP3 MGTHRXN0
AN2 MGTHRXP1
AN1 MGTHRXN1
AL2 MGTHRXP2
AL1 MGTHRXN2
AC10 MGTREFCLK1P
AC9 MGTREFCLK1N
AJ6 MGTHTXP3
AJ5 MGTHTXN3
AK4 MGTHRXP3
AK3 MGTHRXN3
AD8 MGTREFCLK0P
AD7 MGTREFCLK0N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
through Table 3-41 list the five GTH transceiver bank (223-227)
(2)
Schematic Net Name
HDMI_TX0_P
HDMI_TX0_N
HDMI_TX1_P
HDMI_TX1_N
HDMI_TX2_P
HDMI_TX2_N
(1)
HDMI_RX0_C_P
(1)
HDMI_RX0_C_N
(1)
HDMI_RX1_C_P
(1)
HDMI_RX1_C_N
(1)
HDMI_RX2_C_P
(1)
HDMI_RX2_C_N
(1)
HDMI_RX_CLK_C_P
(1)
HDMI_RX_CLK_C_N
FMC_HPC1_DP0_C2M_P
FMC_HPC1_DP0_C2M_N
FMC_HPC1_DP0_M2C_P
FMC_HPC1_DP0_M2C_N
(1)
HDMI_SI5324_OUT_C_P
(1)
HDMI_SI5324_OUT_C_N
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Chapter 3: Board Component Descriptions
Connected To
Pin No. Pin Name
8 IN_D0P
9 IN_D0N
5 IN_D1P
6 IN_D1N
2 IN_D2P
3 IN_D2N
B7 TMDS_DATA0_P
B9 TMDS_DATA0_N
B4 TMDS_DATA1_P
B6 TMDS_DATA1_N
B1 TMDS_DATA2_P
B3 TMDS_DATA2_N
B10 TMDS_CLK_P
B12 TMDS_CLK_N
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
28 CKOUT1_P
29 CKOUT1_N
Device
SN65DP159RGZ HDMI
re-timer U94
P7 MOLEX HDMI
bottom port
FMC HPC1 J4
SI5319C JITTER
ATTEN. U108
95
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