Xilinx ZCU106 User Manual page 132

#Other net PACKAGE_PIN W31
#Other net PACKAGE_PIN AG34 - DR4_SODIMM_DQS8_C
#Other net PACKAGE_PIN AG33 - DR4_SODIMM_DQS8_T
#DDR4 COMPONENT 64-BIT
set_propertyPACKAGE_PIN AK9
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AG11
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AJ10
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AL8
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AK10
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AH8
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AJ9
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AG8
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AH9
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AG10
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AH13
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AG9
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AM13
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AF8
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AC12
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AE12
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AF11
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AK8
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AL12
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AE14
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AB13
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AJ11
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_CK_C"] ;
set_propertyPACKAGE_PIN AH11
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_CK_T"] ;
set_propertyPACKAGE_PIN AC13
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AD14
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AF10
set_propertyIOSTANDARD SSTL12
set_propertyPACKAGE_PIN AF12
set_propertyIOSTANDARD LVCMOS12
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
- DR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7
Bank 504 - PS_DDR_DQS_N8
Bank 504 - PS_DDR_DQS_P8
[get_ports "DDR4_A0"] ;
[get_ports "DDR4_A0"] ;
[get_ports "DDR4_A1"] ;
[get_ports "DDR4_A1"] ;
[get_ports "DDR4_A2"] ;
[get_ports "DDR4_A2"] ;
[get_ports "DDR4_A3"] ;
[get_ports "DDR4_A3"] ;
[get_ports "DDR4_A4"] ;
[get_ports "DDR4_A4"] ;
[get_ports "DDR4_A5"] ;
[get_ports "DDR4_A5"] ;
[get_ports "DDR4_A6"] ;
[get_ports "DDR4_A6"] ;
[get_ports "DDR4_A7"] ;
[get_ports "DDR4_A7"] ;
[get_ports "DDR4_A8"] ;
[get_ports "DDR4_A8"] ;
[get_ports "DDR4_A9"] ;
[get_ports "DDR4_A9"] ;
[get_ports "DDR4_A10"] ;
[get_ports "DDR4_A10"] ;
[get_ports "DDR4_A11"] ;
[get_ports "DDR4_A11"] ;
[get_ports "DDR4_A12"] ;
[get_ports "DDR4_A12"] ;
[get_ports "DDR4_A13"] ;
[get_ports "DDR4_A13"] ;
[get_ports "DDR4_A14_WE_B"] ;
[get_ports "DDR4_A14_WE_B"] ;
[get_ports "DDR4_A15_CAS_B"] ;
[get_ports "DDR4_A15_CAS_B"] ;
[get_ports "DDR4_A16_RAS_B"] ;
[get_ports "DDR4_A16_RAS_B"] ;
[get_ports "DDR4_BA0"] ;
[get_ports "DDR4_BA0"] ;
[get_ports "DDR4_BA1"] ;
[get_ports "DDR4_BA1"] ;
[get_ports "DDR4_BG0"] ;
[get_ports "DDR4_BG0"] ;
[get_ports "DDR4_CKE"] ;
[get_ports "DDR4_CKE"] ;
[get_ports "DDR4_CK_C"] ;
[get_ports "DDR4_CK_T"] ;
[get_ports "DDR4_PAR"] ;
[get_ports "DDR4_PAR"] ;
[get_ports "DDR4_ACT_B"] ;
[get_ports "DDR4_ACT_B"] ;
[get_ports "DDR4_ODT"] ;
[get_ports "DDR4_ODT"] ;
[get_ports "DDR4_RESET_B"] ;
[get_ports "DDR4_RESET_B"] ;
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Appendix B: Master Constraints File Listing
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