Gpio (Mio 13, 38); I2C0 (Mio 14-15) - Xilinx ZCU106 User Manual

GPIO (MIO 13, 38)

These two GPIO bits are connected to the U41 MSP430 system controller for general
purpose signaling or communications between the Zynq UltraScale+ MPSoC device and the
MSP430 system controller. These signals are level-shifted by TSX0108E U141. The
connections between the U41 system controller and the XCZU7EV MPSoC are listed in
Table 3-18.
Table 3-18: System Controller U41 GPIO Connections to XCZU7EV U1
XCZU7EV (U1) Pin
AH17
AL17

I2C0 (MIO 14-15)

I2C0 connects to MPSoC U1 PS bank 500 and PL bank 65, and to system controller U41, as
shown in Figure
U97) and an I2C multiplexer (PCA9544A U60) for controlling resets and power system
enable pins, and accepting various alarm inputs without requiring the PL-side to be
configured. TCA6416A U97 is pin-strapped to respond to I2C address 0x20, and U61 to
0x21. The PCA9544A U60 multiplexer is set to 0x75.
The I2C0 bus also provides access to the PMBus power controllers and PS-side and PL-side
INA226 power monitors via the U60 PCA9544A multiplexer. All PMBus controlled Maxim
regulators are tied to the MAXIM_PMBUS, while the INA226 power monitors are separated
on to PS_PMBUS and PL_PMBUS.
the I2C0 port expander TCA6416A U61 connections and
connections. The devices on each bus of the I2C0 multiplexer U60 are identified in
Table 3-21 and the multiplexer bus connections are listed in
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
MIO13_PS_GPIO2
MIO38_PS_GPIO1
3-18. I2C0 connects to two GPIO 16-bit port expanders (TCA6416A U61 and
Figure 3-17
www.xilinx.com
Chapter 3: Board Component Descriptions
MSP430 U41
Pin Name
20
19
shows the I2C0 bus topology.
Table 3-20 lists the TCA6416A U97
Table 3-22.
Pin #
P1_7
P1_6
Table 3-19 lists
60
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