Xilinx ZCU106 User Manual page 144

set_property IOSTANDARD
set_property PACKAGE_PIN AP11
set_property IOSTANDARD
set_property PACKAGE_PIN AN11
set_property IOSTANDARD
set_property PACKAGE_PIN AP9
set_property IOSTANDARD
set_property PACKAGE_PIN AP10
set_property IOSTANDARD
set_property PACKAGE_PIN AP12
set_property IOSTANDARD
set_property PACKAGE_PIN AN12
set_property IOSTANDARD
#PROTOTYPE MALE PIN HEADER 2X12
set_property PACKAGE_PIN K13
set_property IOSTANDARD
set_property PACKAGE_PIN L14
set_property IOSTANDARD
set_property PACKAGE_PIN J14
set_property IOSTANDARD
set_property PACKAGE_PIN K14
set_property IOSTANDARD
set_property PACKAGE_PIN J11
set_property IOSTANDARD
set_property PACKAGE_PIN K12
set_property IOSTANDARD
set_property PACKAGE_PIN L11
set_property IOSTANDARD
set_property PACKAGE_PIN L12
set_property IOSTANDARD
set_property PACKAGE_PIN G24
set_property IOSTANDARD
set_property PACKAGE_PIN G23
set_property IOSTANDARD
#MSP430 SYSTEM CONTROLLER
set_property PACKAGE_PIN J6
set_property IOSTANDARD
set_property PACKAGE_PIN J7
set_property IOSTANDARD
set_property PACKAGE_PIN J9
set_property IOSTANDARD
set_property PACKAGE_PIN K9
set_property IOSTANDARD
set_property PACKAGE_PIN AA17
set_property IOSTANDARD
set_property PACKAGE_PIN AH16
set_property IOSTANDARD
#SFP
#SFP0
set_property PACKAGE_PIN AE22
set_property IOSTANDARD
set_property PACKAGE_PIN AA1
set_property PACKAGE_PIN AA2
set_property PACKAGE_PIN Y3
set_property PACKAGE_PIN Y4
set_property PACKAGE_PIN AE22
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
LVCMOS12 [get_ports "PMOD1_1_LS"] ;
[get_ports "PMOD1_2_LS"] ;
LVCMOS12 [get_ports "PMOD1_2_LS"] ;
[get_ports "PMOD1_3_LS"] ;
LVCMOS12 [get_ports "PMOD1_3_LS"] ;
[get_ports "PMOD1_4_LS"] ;
LVCMOS12 [get_ports "PMOD1_4_LS"] ;
[get_ports "PMOD1_5_LS"] ;
LVCMOS12 [get_ports "PMOD1_5_LS"] ;
[get_ports "PMOD1_6_LS"] ;
LVCMOS12 [get_ports "PMOD1_6_LS"] ;
[get_ports "PMOD1_7_LS"] ;
LVCMOS12 [get_ports "PMOD1_7_LS"] ;
[get_ports "L6N_AD6N_64_N"] ;
LVCMOS18 [get_ports "L6N_AD6N_64_N"] ;
[get_ports "L6P_AD6P_64_P"] ;
LVCMOS18 [get_ports "L6P_AD6P_64_P"] ;
[get_ports "L5N_AD14N_64_N"] ;
LVCMOS18 [get_ports "L5N_AD14N_64_N"] ;
[get_ports "L5P_AD14P_64_P"] ;
LVCMOS18 [get_ports "L5P_AD14P_64_P"] ;
[get_ports "L4N_AD7N_64_N"] ;
LVCMOS18 [get_ports "L4N_AD7N_64_N"] ;
[get_ports "L4P_AD7P_64_P"] ;
LVCMOS18 [get_ports "L4P_AD7P_64_P"] ;
[get_ports "L3N_AD15N_64_N"] ;
LVCMOS18 [get_ports "L3N_AD15N_64_N"] ;
[get_ports "L3P_AD15P_64_P"] ;
LVCMOS18 [get_ports "L3P_AD15P_64_P"] ;
[get_ports "L14N_HDGC_65_N"] ;
LVDS [get_ports "L14N_HDGC_65_N"] ;
[get_ports "L14P_HDGC_65_P"] ;
LVDS [get_ports "L14P_HDGC_65_P"] ;
[get_ports "MSP430_GPIO_PL_0"] ;
LVCMOS33 [get_ports "MSP430_GPIO_PL_0"] ;
[get_ports "MSP430_GPIO_PL_1"] ;
LVCMOS33 [get_ports "MSP430_GPIO_PL_1"] ;
[get_ports "MSP430_GPIO_PL_2"] ;
LVCMOS33 [get_ports "MSP430_GPIO_PL_2"] ;
[get_ports "MSP430_GPIO_PL_3"] ;
LVCMOS33 [get_ports "MSP430_GPIO_PL_3"] ;
[get_ports "MSP430_UCA1_TXD_LS"] ;
LVCMOS12 [get_ports "MSP430_UCA1_TXD_LS"] ;
[get_ports "MSP430_UCA1_RXD_LS"] ;
LVCMOS12 [get_ports "MSP430_UCA1_RXD_LS"] ;
[get_ports "SFP0_TX_DISABLE"] ;
LVCMOS12 [get_ports "SFP0_TX_DISABLE"] ;
[get_ports "SFP0_RX_N"] ;
[get_ports "SFP0_RX_P"] ;
[get_ports "SFP0_TX_N"] ;
[get_ports "SFP0_TX_P"] ;
[get_ports "SFP0_TX_DISABLE"] ;
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Appendix B: Master Constraints File Listing
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