Xilinx ZCU106 User Manual page 29

The ZCU106 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM socket J1
connections are listed in
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504
XCZU7EV (U1) Pin
AN34
AM34
AM33
AL34
AL33
AK33
AK30
AJ30
AJ31
AH31
AG31
AF31
AG30
AF30
AE27
AE28
AD27
AF27
AP27
AP25
AP26
AM26
AP24
AL25
AM25
AM24
AM28
AN28
AP29
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Table 3-3.
Net Name
DDR4_SODIMM_A0
DDR4_SODIMM_A1
DDR4_SODIMM_A2
DDR4_SODIMM_A3
DDR4_SODIMM_A4
DDR4_SODIMM_A5
DDR4_SODIMM_A6
DDR4_SODIMM_A7
DDR4_SODIMM_A8
DDR4_SODIMM_A9
DDR4_SODIMM_A10
DDR4_SODIMM_A11
DDR4_SODIMM_A12
DDR4_SODIMM_A13
DDR4_SODIMM_BA0
DDR4_SODIMM_BA1
DDR4_SODIMM_BG0
DDR4_SODIMM_BG1
DDR4_SODIMM_DQ0
DDR4_SODIMM_DQ1
DDR4_SODIMM_DQ2
DDR4_SODIMM_DQ3
DDR4_SODIMM_DQ4
DDR4_SODIMM_DQ5
DDR4_SODIMM_DQ6
DDR4_SODIMM_DQ7
DDR4_SODIMM_DQ8
DDR4_SODIMM_DQ9
DDR4_SODIMM_DQ10
www.xilinx.com
Chapter 3: Board Component Descriptions
DDR4 SODIMM Memory J1
Pin Number
144
133
132
131
128
126
127
122
125
121
146
120
119
158
150
145
115
113
8
7
20
21
4
3
16
17
28
29
41
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Pin Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
BA0
BA1
BG0
BG1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
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