Xilinx ZCU106 User Manual page 58

CP2108 Channel 2 PL-Side UART Interface
The CP2108 channel 2 bank 64 PL-side UART interface circuit is shown in
connections from XCZU7EV MPSoC U1 to CP2108 U40 via TSX0104E level shifter U52 are
listed in Table
X-Ref Target - Figure 3-15
Table 3-16: XCZU7EV U1 to CP2108 U40 Connections via L/S U52
XCZU7EV (U1)
Pin
AH17
AL17
AM15
AP17
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
3-16.
Figure 3-15: PL-Side USB UART Interface
Net Name
UART2_TXD_O_FPGA_RXD
UART2_RXD_I_FPGA_TXD
UART2_RTS_O_B
UART2_RTS_I_B
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Chapter 3: Board Component Descriptions
CP2108 U40
Pin Name
TX_2
RX_2
RTS_2
CTS_2
Send Feedback
Figure 3-15. The
X19177-050117
Pin #
16
15
14
13
58