Xilinx ZCU106 User Manual page 146

#UART
set_property PACKAGE_PIN AH17
set_property IOSTANDARD
set_property PACKAGE_PIN AM15
set_property IOSTANDARD
set_property PACKAGE_PIN AL17
set_property IOSTANDARD
set_property PACKAGE_PIN AP17
set_property IOSTANDARD
#SDI VIDEO
set_property PACKAGE_PIN B21
set_property IOSTANDARD
set_property PACKAGE_PIN H23
set_property IOSTANDARD
set_property PACKAGE_PIN L21
set_property IOSTANDARD
set_property PACKAGE_PIN A9
set_property IOSTANDARD
set_property PACKAGE_PIN J20
set_property IOSTANDARD
set_property PACKAGE_PIN J19
set_property IOSTANDARD
set_property PACKAGE_PIN E13
set_property IOSTANDARD
set_property PACKAGE_PIN C14
set_property IOSTANDARD
set_property PACKAGE_PIN AC1
set_property PACKAGE_PIN AC2
set_property PACKAGE_PIN AC5
set_property PACKAGE_PIN AC6
#AES3 AUDIO
set_property PACKAGE_PIN G7
set_property IOSTANDARD
set_property PACKAGE_PIN AF13
set_property IOSTANDARD
set_property PACKAGE_PIN AE13
set_property IOSTANDARD
#PCIE
set_property PACKAGE_PIN L8
set_property IOSTANDARD
set_property PACKAGE_PIN L10
set_property IOSTANDARD
#PS GTR BANK 505
#Other net PACKAGE_PIN U30 - GT0_DP_TX_N
#Other net PACKAGE_PIN R30 - GT1_DP_TX_N
#Other net PACKAGE_PIN U29 - GT0_DP_TX_P
#Other net PACKAGE_PIN R29 - GT1_DP_TX_P
#Other net PACKAGE_PIN R34 - GT2_USB0_RX_N
#Other net PACKAGE_PIN R33 - GT2_USB0_RX_P
#Other net PACKAGE_PIN P32 - GT2_USB0_TX_N
#Other net PACKAGE_PIN P31 - GT2_USB0_TX_P
#Other net PACKAGE_PIN N34 - GT3_SATA1_RX_N Bank 505 - PS_MGTRRXN3_505
#Other net PACKAGE_PIN N33 - GT3_SATA1_RX_P Bank 505 - PS_MGTRRXP3_505
#Other net PACKAGE_PIN N30 - GT3_SATA1_TX_N Bank 505 - PS_MGTRTXN3_505
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "UART2_TXD_O_FPGA_RXD"] ;
LVCMOS12 [get_ports "UART2_TXD_O_FPGA_RXD"] ;
[get_ports "UART2_RTS_O_B"] ;
LVCMOS12 [get_ports "UART2_RTS_O_B"] ;
[get_ports "UART2_RXD_I_FPGA_TXD"] ;
LVCMOS12 [get_ports "UART2_RXD_I_FPGA_TXD"] ;
[get_ports "UART2_CTS_I_B"] ;
LVCMOS12 [get_ports "UART2_CTS_I_B"] ;
[get_ports "SDI_SCLK_LS"] ;
LVCMOS18 [get_ports "SDI_SCLK_LS"] ;
[get_ports "SDI_MISO_LS"] ;
LVCMOS18 [get_ports "SDI_MISO_LS"] ;
[get_ports "SDI_MOSI_LS"] ;
LVCMOS18 [get_ports "SDI_MOSI_LS"] ;
[get_ports "SDI_CS_RCLKR_LS"] ;
LVCMOS18 [get_ports "SDI_CS_RCLKR_LS"] ;
[get_ports "SDI_CS_RCVR_LS"] ;
LVCMOS18 [get_ports "SDI_CS_RCVR_LS"] ;
[get_ports "SDI_CS_DRVR_LS"] ;
LVCMOS18 [get_ports "SDI_CS_DRVR_LS"] ;
[get_ports "SDI_XALARM_RX_LS"] ;
LVCMOS18 [get_ports "SDI_XALARM_RX_LS"] ;
[get_ports "SDI_XALARM_TX_LS"] ;
LVCMOS18 [get_ports "SDI_XALARM_TX_LS"] ;
[get_ports "SDI_MGT_RX_N"] ;
[get_ports "SDI_MGT_RX_P"] ;
[get_ports "SDI_MGT_TX_N"] ;
[get_ports "SDI_MGT_TX_P"] ;
[get_ports "AES_IN"] ;
LVCMOS33 [get_ports "AES_IN"] ;
[get_ports "AES_OUT_N"] ;
DIFF_SSTL12 [get_ports "AES_OUT_N"] ;
[get_ports "AES_OUT_P"] ;
DIFF_SSTL12 [get_ports "AES_OUT_P"] ;
[get_ports "PCIE_PERST_B"] ;
LVCMOS33 [get_ports "PCIE_PERST_B"] ;
[get_ports "PCIE_WAKE_B"] ;
LVCMOS33 [get_ports "PCIE_WAKE_B"] ;
Bank 505 - PS_MGTRTXN0_505
Bank 505 - PS_MGTRTXN1_505
Bank 505 - PS_MGTRTXP0_505
Bank 505 - PS_MGTRTXP1_505
Bank 505 - PS_MGTRRXN2_505
Bank 505 - PS_MGTRRXP2_505
Bank 505 - PS_MGTRTXN2_505
Bank 505 - PS_MGTRTXP2_505
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Appendix B: Master Constraints File Listing
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