Sfp/Sfp+ Clock Recovery - Xilinx ZCU106 User Manual

Table 3-32: ZCU106 FPGA U1 to SFP0 and SFP1 Module Connections
XCZU7EV (U1) Pin
Y4
Y3
AA2
AA1
AE22
W6
W5
W2
W1
AF20
Notes:
1. SFPx_TX_DISABLE_B nets implement the LVCMOS33 standard.

SFP/SFP+ Clock Recovery

[Figure 2-1, callout 11]
The ZCU106 board includes a Silicon Labs Si5328B jitter attenuator U20 (8 kHz – 808 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 68
(SFP_REC_CLOCK_C_P, pin H11 and SFP_REC_CLOCK_C_N, pin G11) for jitter attenuation. The
jitter attenuated clock (SFP_SI5328_OUT_C_P (U20 pin 28), SFP_SI5328_OUT_C_N (U20 pin
29)) is then routed as a series capacitor coupled reference clock to GTH Quad 225 inputs
MGTREFCLK1P (U1 pin W10) and MGTREFCLK1N (U1 pin W9).
The primary purpose of this clock is to support synchronous protocols such as CPRI or
OBSAI to perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter
attenuated recovered clock to drive the reference clock inputs of a GTH transceiver. The
system controller configures the SI5328B in free-run mode (see
Controller, page
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Net Name
SFP0_TX_P
SFP0_TX_N
SFP0_RX_P
SFP0_RX_N
SFP0_TX_DISABLE_B
SFP1_TX_P
SFP1_TX_N
SFP1_RX_P
SFP1_RX_N
SFP1_TX_DISABLE_B
116). The jitter attenuated clock circuit is shown in
www.xilinx.com
Chapter 3: Board Component Descriptions
Pin No. Pin Name
18 TD_P
19 TD_N
13 RD_P
12 RD_N
3 TX_DISABLE
18 TD_P
19 TD_N
13 RD_P
12 RD_N
3 TX_DISABLE
SFP/SFP+ Module
P1
P2
TI MSP430 System
Figure 3-30.
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