Xilinx ZCU106 User Manual page 136

set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS7_T"] ;
#QSPI
#QSPI_LWR U119 and UPR U120 are connected to PS MIO Bank 500
#Other net PACKAGE_PIN A24 - MIO0_QSPI_LWR_CLK
#Other net PACKAGE_PIN C24 - MIO1_QSPI_LWR_DQ1
#Other net PACKAGE_PIN B24 - MIO2_QSPI_LWR_DQ2
#Other net PACKAGE_PIN E25 - MIO3_QSPI_LWR_DQ3
#Other net PACKAGE_PIN A25 - MIO4_QSPI_LWR_DQ0
#Other net PACKAGE_PIN D25 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5
#Other net PACKAGE_PIN B25 - MIO7_QSPI_UPR_CS_B Bank 500 - PS_MIO7
#Other net PACKAGE_PIN D26 - MIO8_QSPI_UPR_DQ0
#Other net PACKAGE_PIN C26 - MIO9_QSPI_UPR_DQ1
#Other net PACKAGE_PIN F26 - MIO10_QSPI_UPR_DQ2 Bank 500 - PS_MIO10
#Other net PACKAGE_PIN B26 - MIO11_QSPI_UPR_DQ3 Bank 500 - PS_MIO11
#Other net PACKAGE_PIN C27 - MIO12_QSPI_UPR_CLK Bank 500 - PS_MIO12
#FMC
#HPC0 J5
set_propertyPACKAGE_PIN E14
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E15
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F10
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G10
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN V7
set_propertyPACKAGE_PIN V8
set_propertyPACKAGE_PIN T7
set_propertyPACKAGE_PIN T8
set_propertyPACKAGE_PIN R5
set_propertyPACKAGE_PIN R6
set_propertyPACKAGE_PIN R1
set_propertyPACKAGE_PIN R2
set_propertyPACKAGE_PIN T3
set_propertyPACKAGE_PIN T4
set_propertyPACKAGE_PIN U1
set_propertyPACKAGE_PIN U2
set_propertyPACKAGE_PIN N5
set_propertyPACKAGE_PIN N6
set_propertyPACKAGE_PIN P3
set_propertyPACKAGE_PIN P4
set_propertyPACKAGE_PIN U5
set_propertyPACKAGE_PIN U6
set_propertyPACKAGE_PIN V3
set_propertyPACKAGE_PIN V4
set_propertyPACKAGE_PIN H3
set_propertyPACKAGE_PIN H4
set_propertyPACKAGE_PIN G1
set_propertyPACKAGE_PIN G2
set_propertyPACKAGE_PIN L5
set_propertyPACKAGE_PIN L6
set_propertyPACKAGE_PIN L1
set_propertyPACKAGE_PIN L2
set_propertyPACKAGE_PIN M3
set_propertyPACKAGE_PIN M4
set_propertyPACKAGE_PIN N1
set_propertyPACKAGE_PIN N2
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "FMC_HPC0_CLK0_M2C_N"] ;
LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"] ;
[get_ports "FMC_HPC0_CLK0_M2C_P"] ;
LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"] ;
[get_ports "FMC_HPC0_CLK1_M2C_N"] ;
LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"] ;
[get_ports "FMC_HPC0_CLK1_M2C_P"] ;
LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"] ;
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;
[get_ports "FMC_HPC0_DP0_C2M_N"] ;
[get_ports "FMC_HPC0_DP0_C2M_P"] ;
[get_ports "FMC_HPC0_DP0_M2C_N"] ;
[get_ports "FMC_HPC0_DP0_M2C_P"] ;
[get_ports "FMC_HPC0_DP1_C2M_N"] ;
[get_ports "FMC_HPC0_DP1_C2M_P"] ;
[get_ports "FMC_HPC0_DP1_M2C_N"] ;
[get_ports "FMC_HPC0_DP1_M2C_P"] ;
[get_ports "FMC_HPC0_DP2_C2M_N"] ;
[get_ports "FMC_HPC0_DP2_C2M_P"] ;
[get_ports "FMC_HPC0_DP2_M2C_N"] ;
[get_ports "FMC_HPC0_DP2_M2C_P"] ;
[get_ports "FMC_HPC0_DP3_C2M_N"] ;
[get_ports "FMC_HPC0_DP3_C2M_P"] ;
[get_ports "FMC_HPC0_DP3_M2C_N"] ;
[get_ports "FMC_HPC0_DP3_M2C_P"] ;
[get_ports "FMC_HPC0_DP4_C2M_N"] ;
[get_ports "FMC_HPC0_DP4_C2M_P"] ;
[get_ports "FMC_HPC0_DP4_M2C_N"] ;
[get_ports "FMC_HPC0_DP4_M2C_P"] ;
[get_ports "FMC_HPC0_DP5_C2M_N"] ;
[get_ports "FMC_HPC0_DP5_C2M_P"] ;
[get_ports "FMC_HPC0_DP5_M2C_N"] ;
[get_ports "FMC_HPC0_DP5_M2C_P"] ;
[get_ports "FMC_HPC0_DP6_C2M_N"] ;
[get_ports "FMC_HPC0_DP6_C2M_P"] ;
[get_ports "FMC_HPC0_DP6_M2C_N"] ;
[get_ports "FMC_HPC0_DP6_M2C_P"] ;
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Appendix B: Master Constraints File Listing
Bank 500 - PS_MIO0
Bank 500 - PS_MIO1
Bank 500 - PS_MIO2
Bank 500 - PS_MIO3
Bank 500 - PS_MIO4
Bank 500 - PS_MIO8
Bank 500 - PS_MIO9
136
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