Xilinx ZCU106 User Manual page 141

set_property PACKAGE_PIN F13
set_property IOSTANDARD
set_property PACKAGE_PIN G14
set_property IOSTANDARD
set_property PACKAGE_PIN F21
set_property IOSTANDARD
set_property PACKAGE_PIN G21
set_property IOSTANDARD
set_property PACKAGE_PIN AC9
set_property PACKAGE_PIN AC10
set_property PACKAGE_PIN M8
set_property IOSTANDARD
set_property PACKAGE_PIN M10
set_property IOSTANDARD
set_property PACKAGE_PIN M9
set_property IOSTANDARD
set_property PACKAGE_PIN M11
set_property IOSTANDARD
set_property PACKAGE_PIN N11
set_property IOSTANDARD
set_property PACKAGE_PIN M12
set_property IOSTANDARD
set_property PACKAGE_PIN N13
set_property IOSTANDARD
set_property PACKAGE_PIN N8
set_property IOSTANDARD
set_property PACKAGE_PIN N9
set_property IOSTANDARD
set_property PACKAGE_PIN N12
set_property IOSTANDARD
set_property PACKAGE_PIN P12
set_property IOSTANDARD
set_property PACKAGE_PIN G8
set_property IOSTANDARD
set_property PACKAGE_PIN H8
set_property IOSTANDARD
#HDMI CLOCK RECOVERY
set_property PACKAGE_PIN F13
set_property IOSTANDARD
set_property PACKAGE_PIN G14
set_property IOSTANDARD
#ARM TRACE
set_property PACKAGE_PIN H6
set_property IOSTANDARD
set_property PACKAGE_PIN G6
set_property IOSTANDARD
set_property PACKAGE_PIN H7
set_property IOSTANDARD
set_property PACKAGE_PIN E1
set_property IOSTANDARD
set_property PACKAGE_PIN D1
set_property IOSTANDARD
set_property PACKAGE_PIN C1
set_property IOSTANDARD
set_property PACKAGE_PIN B1
set_property IOSTANDARD
set_property PACKAGE_PIN A3
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "HDMI_REC_CLOCK_C_N"] ;
LVDS [get_ports "HDMI_REC_CLOCK_C_N"] ;
[get_ports "HDMI_REC_CLOCK_C_P"] ;
LVDS [get_ports "HDMI_REC_CLOCK_C_P"] ;
[get_ports "HDMI_TX_LVDS_OUT_N"] ;
LVDS [get_ports "HDMI_TX_LVDS_OUT_N"] ;
[get_ports "HDMI_TX_LVDS_OUT_P"] ;
LVDS [get_ports "HDMI_TX_LVDS_OUT_P"] ;
[get_ports "HDMI_RX_CLK_C_N"] ;
[get_ports "HDMI_RX_CLK_C_P"] ;
[get_ports "HDMI_RX_PWR_DET"] ;
LVCMOS33 [get_ports "HDMI_RX_PWR_DET"] ;
[get_ports "HDMI_RX_HPD"] ;
LVCMOS33 [get_ports "HDMI_RX_HPD"] ;
[get_ports "HDMI_RX_SNK_SCL"] ;
LVCMOS33 [get_ports "HDMI_RX_SNK_SCL"] ;
[get_ports "HDMI_RX_SNK_SDA"] ;
LVCMOS33 [get_ports "HDMI_RX_SNK_SDA"] ;
[get_ports "HDMI_TX_EN"] ;
LVCMOS33 [get_ports "HDMI_TX_EN"] ;
[get_ports "HDMI_TX_CEC"] ;
LVCMOS33 [get_ports "HDMI_TX_CEC"] ;
[get_ports "HDMI_TX_HPD"] ;
LVCMOS33 [get_ports "HDMI_TX_HPD"] ;
[get_ports "HDMI_TX_SRC_SCL"] ;
LVCMOS33 [get_ports "HDMI_TX_SRC_SCL"] ;
[get_ports "HDMI_TX_SRC_SDA"] ;
LVCMOS33 [get_ports "HDMI_TX_SRC_SDA"] ;
[get_ports "HDMI_CTL_SCL"] ;
LVCMOS33 [get_ports "HDMI_CTL_SCL"] ;
[get_ports "HDMI_CTL_SDA"] ;
LVCMOS33 [get_ports "HDMI_CTL_SDA"] ;
[get_ports "HDMI_SI5324_LOL"] ;
LVCMOS33 [get_ports "HDMI_SI5324_LOL"] ;
[get_ports "HDMI_SI5324_RST"] ;
LVCMOS33 [get_ports "HDMI_SI5324_RST"] ;
[get_ports "HDMI_REC_CLOCK_C_N"] ;
LVDS [get_ports "HDMI_REC_CLOCK_C_N"] ;
[get_ports "HDMI_REC_CLOCK_C_P"] ;
LVDS [get_ports "HDMI_REC_CLOCK_C_P"] ;
[get_ports "TRACEDATA0"] ;
LVCMOS33 [get_ports "TRACEDATA0"] ;
[get_ports "TRACEDATA1"] ;
LVCMOS33 [get_ports "TRACEDATA1"] ;
[get_ports "TRACEDATA2"] ;
LVCMOS33 [get_ports "TRACEDATA2"] ;
[get_ports "TRACEDATA3"] ;
LVCMOS33 [get_ports "TRACEDATA3"] ;
[get_ports "TRACEDATA4"] ;
LVCMOS33 [get_ports "TRACEDATA4"] ;
[get_ports "TRACEDATA5"] ;
LVCMOS33 [get_ports "TRACEDATA5"] ;
[get_ports "TRACEDATA6"] ;
LVCMOS33 [get_ports "TRACEDATA6"] ;
[get_ports "TRACEDATA7"] ;
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Appendix B: Master Constraints File Listing
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