Xilinx ZCU106 User Manual page 137

set_propertyPACKAGE_PIN K3
set_propertyPACKAGE_PIN K4
set_propertyPACKAGE_PIN J1
set_propertyPACKAGE_PIN J2
set_propertyPACKAGE_PIN F16
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN L20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN L16
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN L17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J15
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J16
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E17
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G16
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H16
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN K15
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN L15
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A12
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A13
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F15
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G15
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "FMC_HPC0_DP7_C2M_N"] ;
[get_ports "FMC_HPC0_DP7_C2M_P"] ;
[get_ports "FMC_HPC0_DP7_M2C_N"] ;
[get_ports "FMC_HPC0_DP7_M2C_P"] ;
[get_ports "FMC_HPC0_LA00_CC_N"] ;
LVDS [get_ports "FMC_HPC0_LA00_CC_N"] ;
[get_ports "FMC_HPC0_LA00_CC_P"] ;
LVDS [get_ports "FMC_HPC0_LA00_CC_P"] ;
[get_ports "FMC_HPC0_LA01_CC_N"] ;
LVDS [get_ports "FMC_HPC0_LA01_CC_N"] ;
[get_ports "FMC_HPC0_LA01_CC_P"] ;
LVDS [get_ports "FMC_HPC0_LA01_CC_P"] ;
[get_ports "FMC_HPC0_LA02_N"] ;
LVDS [get_ports "FMC_HPC0_LA02_N"] ;
[get_ports "FMC_HPC0_LA02_P"] ;
LVDS [get_ports "FMC_HPC0_LA02_P"] ;
[get_ports "FMC_HPC0_LA03_N"] ;
LVDS [get_ports "FMC_HPC0_LA03_N"] ;
[get_ports "FMC_HPC0_LA03_P"] ;
LVDS [get_ports "FMC_HPC0_LA03_P"] ;
[get_ports "FMC_HPC0_LA04_N"] ;
LVDS [get_ports "FMC_HPC0_LA04_N"] ;
[get_ports "FMC_HPC0_LA04_P"] ;
LVDS [get_ports "FMC_HPC0_LA04_P"] ;
[get_ports "FMC_HPC0_LA05_N"] ;
LVDS [get_ports "FMC_HPC0_LA05_N"] ;
[get_ports "FMC_HPC0_LA05_P"] ;
LVDS [get_ports "FMC_HPC0_LA05_P"] ;
[get_ports "FMC_HPC0_LA06_N"] ;
LVDS [get_ports "FMC_HPC0_LA06_N"] ;
[get_ports "FMC_HPC0_LA06_P"] ;
LVDS [get_ports "FMC_HPC0_LA06_P"] ;
[get_ports "FMC_HPC0_LA07_N"] ;
LVDS [get_ports "FMC_HPC0_LA07_N"] ;
[get_ports "FMC_HPC0_LA07_P"] ;
LVDS [get_ports "FMC_HPC0_LA07_P"] ;
[get_ports "FMC_HPC0_LA08_N"] ;
LVDS [get_ports "FMC_HPC0_LA08_N"] ;
[get_ports "FMC_HPC0_LA08_P"] ;
LVDS [get_ports "FMC_HPC0_LA08_P"] ;
[get_ports "FMC_HPC0_LA09_N"] ;
LVDS [get_ports "FMC_HPC0_LA09_N"] ;
[get_ports "FMC_HPC0_LA09_P"] ;
LVDS [get_ports "FMC_HPC0_LA09_P"] ;
[get_ports "FMC_HPC0_LA10_N"] ;
LVDS [get_ports "FMC_HPC0_LA10_N"] ;
[get_ports "FMC_HPC0_LA10_P"] ;
LVDS [get_ports "FMC_HPC0_LA10_P"] ;
[get_ports "FMC_HPC0_LA11_N"] ;
LVDS [get_ports "FMC_HPC0_LA11_N"] ;
[get_ports "FMC_HPC0_LA11_P"] ;
LVDS [get_ports "FMC_HPC0_LA11_P"] ;
[get_ports "FMC_HPC0_LA12_N"] ;
LVDS [get_ports "FMC_HPC0_LA12_N"] ;
[get_ports "FMC_HPC0_LA12_P"] ;
LVDS [get_ports "FMC_HPC0_LA12_P"] ;
[get_ports "FMC_HPC0_LA13_N"] ;
LVDS [get_ports "FMC_HPC0_LA13_N"] ;
[get_ports "FMC_HPC0_LA13_P"] ;
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Appendix B: Master Constraints File Listing
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