Xilinx ZCU106 User Manual page 129

#USER_SI570 300 MHz
set_property PACKAGE_PIN AJ12
set_property IOSTANDARD
set_property PACKAGE_PIN AH12
set_property IOSTANDARD
#For completeness, the MGT clocks are documented here:
#MGTH 223 HDMI I/F
set_property PACKAGE_PIN AD7
set_property PACKAGE_PIN AD8
set_property PACKAGE_PIN AC9
set_property PACKAGE_PIN AC10
#MGTH 224 PCIE I/F
set_property PACKAGE_PIN AB7
set_property PACKAGE_PIN AB8
#MGTH 225 SDI, SMA_MGT, SFP0/1 I/F
set_property PACKAGE_PIN Y7
set_property PACKAGE_PIN Y8
set_property PACKAGE_PIN W9
set_property PACKAGE_PIN W10
#MGTH 226 HPC0 I/F
set_property PACKAGE_PIN V7
set_property PACKAGE_PIN V8
set_property PACKAGE_PIN U9
set_property PACKAGE_PIN U10
#MGTH 227 HPC0 I/F
set_property PACKAGE_PIN T7
set_property PACKAGE_PIN T8
set_property PACKAGE_PIN R9
set_property PACKAGE_PIN R10
#GTR 505 FIXED CLOCKS SOURCED FROM U69 SI5341B
#Other net PACKAGE_PIN P28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505
#Other net PACKAGE_PIN P27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505
#Other net PACKAGE_PIN M28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505
#Other net PACKAGE_PIN M27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505
#Other net PACKAGE_PIN M32 - GTR_REF_CLK_DP_C_N
#Other net PACKAGE_PIN M31 - GTR_REF_CLK_DP_C_P
#MEMORY
#DDR4 SODIMM J1 is a PS DDR Bank 504 Interface
#Other net PACKAGE_PIN AN34 - DR4_SODIMM_A0
#Other net PACKAGE_PIN AM34 - DR4_SODIMM_A1
#Other net PACKAGE_PIN AM33 - DR4_SODIMM_A2
#Other net PACKAGE_PIN AL34 - DR4_SODIMM_A3
#Other net PACKAGE_PIN AL33 - DR4_SODIMM_A4
#Other net PACKAGE_PIN AK33 - DR4_SODIMM_A5
#Other net PACKAGE_PIN AK30 - DR4_SODIMM_A6
#Other net PACKAGE_PIN AJ30 - DR4_SODIMM_A7
#Other net PACKAGE_PIN AJ31 - DR4_SODIMM_A8
#Other net PACKAGE_PIN AH31 - DR4_SODIMM_A9
#Other net PACKAGE_PIN AG31 - DR4_SODIMM_A10
#Other net PACKAGE_PIN AF31 - DR4_SODIMM_A11
#Other net PACKAGE_PIN AG30 - DR4_SODIMM_A12
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "USER_SI570_N"] ;
DIFF_SSTL12 [get_ports "USER_SI570_N"] ;
[get_ports "USER_SI570_P"] ;
DIFF_SSTL12 [get_ports "USER_SI570_P"] ;
[get_ports "HDMI_SI5324_OUT_C_N"]
[get_ports "HDMI_SI5324_OUT_C_P"]
[get_ports "HDMI_RX_CLK_C_N"] ;
[get_ports "HDMI_RX_CLK_C_P"] ;
[get_ports "PCIE_CLK_N"] ;
[get_ports "PCIE_CLK_P"] ;
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;
[get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;
[get_ports "SFP_SI5328_OUT_C_N"] ;
[get_ports "SFP_SI5328_OUT_C_P"] ;
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;
[get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;
[get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;
[get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;
[get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;
[get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;
[get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;
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Appendix B: Master Constraints File Listing
Bank 505 - PS_MGTREFCLK3N_505
Bank 505 - PS_MGTREFCLK3P_505
Bank 504 - PS_DDR_A0
Bank 504 - PS_DDR_A1
Bank 504 - PS_DDR_A2
Bank 504 - PS_DDR_A3
Bank 504 - PS_DDR_A4
Bank 504 - PS_DDR_A5
Bank 504 - PS_DDR_A6
Bank 504 - PS_DDR_A7
Bank 504 - PS_DDR_A8
Bank 504 - PS_DDR_A9
Bank 504 - PS_DDR_A10
Bank 504 - PS_DDR_A11
Bank 504 - PS_DDR_A12
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