Xilinx ZCU106 User Manual page 98

Table 3-40: GTH Transceiver Bank 226 Interface Connections
XCZU7EV XCZU7EV Pin
(U1) Pin Name
U6 MGTHTXP0
U5 MGTHTXN0
V4 MGTHRXP0
V3 MGTHRXN0
T4 MGTHTXP1
T3 MGTHTXN1
U2 MGTHRXP1
U1 MGTHRXN1
R6 MGTHTXP2
R5 MGTHTXN2
R2 MGTHRXP2
R1 MGTHRXN2
N6 MGTHTXP3
N5 MGTHTXN3
P4 MGTHRXP3
P3 MGTHRXN3
V8 MGTREFCLK0P
V7 MGTREFCLK0N
U10 MGTREFCLK1P
U9 MGTREFCLK1N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Schematic Net Name
FMC_HPC0_DP3_C2M_P
FMC_HPC0_DP3_C2M_N
FMC_HPC0_DP3_M2C_P
FMC_HPC0_DP3_M2C_N
FMC_HPC0_DP1_C2M_P
FMC_HPC0_DP1_C2M_N
FMC_HPC0_DP1_M2C_P
FMC_HPC0_DP1_M2C_N
FMC_HPC0_DP0_C2M_P
FMC_HPC0_DP0_C2M_N
FMC_HPC0_DP0_M2C_P
FMC_HPC0_DP0_M2C_N
FMC_HPC0_DP2_C2M_P
FMC_HPC0_DP2_C2M_N
FMC_HPC0_DP2_M2C_P
FMC_HPC0_DP2_M2C_N
FMC_HPC0_GBTCLK0_M2C_C_P
FMC_HPC0_GBTCLK0_M2C_C_N
USER_MGT_SI570_CLOCK1_C_P
USER_MGT_SI570_CLOCK1_C_N
www.xilinx.com
Chapter 3: Board Component Descriptions
(2)
Pin No. Pin Name
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
A11 DP3_M2C_N
A22 DP1_C2M_P
A23 DP1_C2M_N
A2 DP1_M2C_P
A3 DP1_M2C_N
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
A7 DP2_M2C_N
(1)
D4 GBTCLK0_M2C_P
(1)
D5 GBTCLK0_M2C_N
(1)
11 Q1_P
(1)
12 Q1_N
Connected To
Device
FMC HPC0 J5
SI53340 U51
1-to-2 buffer
Send Feedback
98