Clock Generation - Xilinx AC701 User Manual

X-Ref Target - Figure 1-9
VCC3V3
U26
Digilent
USB-JTAG
Module
R95 15Ω
TDI
R96 15Ω
TMS
R94 15Ω
TCK
TDO
VCC3V3
J4
JTAG
Header
JTAG_TDI
TDI
JTAG_TMS
TMS
JTAG_TCK
TCK
JTAG_TDO
TDO

Clock Generation

There are three clock sources available for the FPGA fabric on the AC701 board (refer to
Table
Table 1-8: AC701 Board Clock Sources
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
U19
SN74LV541A
Buffer
Figure 1-9: JTAG Circuit
1-8).
Clock Name Reference
System Clock
User Clock
User SMA Clock
(differential pair)
www.xilinx.com
VCC3V3
U27
SiT9102 2.5V LVDS 200 MHz Fixed Frequency
U51
Oscillator (Si Time). See
Si570 3.3V LVDS I
U34 (Silicon Labs). Default power-on frequency 156.250
MHz. See Programmable User Clock Source, page
USER_SMA_CLOCK_P (net name).
J31
See User SMA Clock Input, page
USER_SMA_CLOCK_N (net name)
J32
See User SMA Clock Input, page 24
Feature Descriptions
J30
FMC1 HPC
Connector
FMC1_HPC_PRSNT_M2C_B
PRSNT_L
FMC_TDI_BUF
TDI
FMC1_TDO_FPGA_TDI
TDO
FMC1_HPC_TMS_BUF
TMS
FMC1_HPC_TCK_BUF
TCK
U1
Artix-7
FPGA
Bank 14
N16
Bank 0
FPGA_TDI_BUF
TDI
FPGA_TCK_BUF
TCK
FPGA_TMS_BUF
TMS
FPGA_TDO
TDO
UG952_c1_09_101512
Description
System Clock Source, page
2
C Programmable Oscillator
24.
22.
23.
21