Platform Management Unit Gpi (Mio 26); Displayport Dpaux (Mio 27-30) - Xilinx ZCU106 User Manual

X-Ref Target - Figure 3-21
CANH_TERM

Platform Management Unit GPI (MIO 26)

PS-side MIO 26 is reserved as an input to the platform management unit (PMU) for
indicating a warm boot. PS bank 501 MIO26 (U1.A29) is connected to the I2C0 U61
TCA6416APWR bus expander (port P04 U61.8) through L/S U147 SN74AVC1T45. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
the PMU interface.

DisplayPort DPAUX (MIO 27-30)

The Zynq UltraScale+ MPSoC provides a VESA DisplayPort 1.2 source-only controller that
supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The
DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb/s data
rate, which is translated from single-ended MIO signals to the differential DisplayPort AUX
channel, DPAUX (see
Table 3-27: DPAUX/MIO Connections
XCZU7EV (U1) Pin
A33
A32
A31
A30
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
J98
GND GND
CANL_TERM
CANL CANH
Figure 3-21: PS-Side CAN Bus Interface Connector
Table 3-27). The DisplayPort circuit is shown in
Net Name
MIO30_DP_AUX_IN
MIO29_DP_OE
MIO28_DP_HPD
MIO27_DP_AUX_OUT
www.xilinx.com
Chapter 3: Board Component Descriptions
CANH_TERM CANL_TERM
60Ω
4700 pF
[Ref 2]
Level Shifter U114
Pin Name
2A1
1A2
2A2
1A1
60Ω
X16534-052417
for more details on
Figure 3-22.
Pin #
8
7
9
6
69
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