Xilinx ZCU106 User Manual page 103

Bank 505 DP (DisplayPort) lanes 0 and 1 TX support the 2-channel source only PS-side
DisplayPort circuitry described in
Bank 505 USB0 lane 2 supports the USB3.0 interface described in
USB 2.0 ULPI PHY, page
Bank 505 SATA1 lane 3 supports SATA connector P9 as shown in
X-Ref Target - Figure 3-42
Bank 505 reference clocks are connected to the U69 SI5341B clock generator as described
in SI5341B 10 Independent Output Any-Frequency Clock Generator, page
connections are shown in
Table 3-42: PS-GTR Bank 505 Interface Connections
XCZU7EV
(U1) Pin XCZU7EV Pin Name
U29 PS_MGTRTXP0
U30 PS_MGTRTXN0
R29 PS_MGTRTXP1
R30 PS_MGTRTXN1
U33 PS_MGTRRXP0
U34 PS_MGTRRXN0
T31 PS_MGTRRXP1
T32 PS_MGTRRXN1
P31 PS_MGTRTXP2
P32 PS_MGTRTXN2
R33 PS_MGTRRXP2
R34 PS_MGTRRXN2
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
DisplayPort DPAUX (MIO 27-30), page
40.
Figure 3-42: PS-GTR SATA
Table 3-42.
(2)
Schematic Net Name
(1)
GT0_DP_TX_P
(1)
GT0_DP_TX_N
(1)
GT1_DP_TX_P
(1)
GT1_DP_TX_N
NC
NC
NC
NC
(1)
GT2_USB0_TX_P
(1)
GT2_USB0_TX_N
GT2_USB0_RX_P
GT2_USB0_RX_N
www.xilinx.com
Chapter 3: Board Component Descriptions
USB 3.0 Transceiver and
Figure
Connected To
Pin No. Pin Name
4 ML_LANE1_P
6 ML_LANE1_N
1 ML_LANE0_P
3 ML_LANE0_N
NA NA
NA NA
NA NA
NA NA
9 SSTXP
8 SSTXN
6 SSRXP
5 SSRXN
69.
3-42.
X19202-050117
50. Bank 505
Device
DisplayPort
connector P11
NA
USB J96
103
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