Fmc Connector Jtag Bypass; Clock Generation - Xilinx ZC702 User Manual

DIP switch SW10[1:2] setting 10 selects the 14-pin header J2 for configuration using either
a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW10 setting 01 selects the
USB-to-JTAG Digilent bridge U23 for configuration over a Standard-A to Micro-B USB cable.
DIP switch SW10 setting 11 selects the JTAG 20-pin header at J58. The four JTAG signals TDI,
TDO, TCK, and TMS would be connected to J58 through flying leads from a JTAG cable. The
3-to-1 analog switch settings are shown in
Table 1-10: Switch SW10 JTAG Configuration Option Settings
Configuration Source
None
Digilent USB-to-JTAG interface U23
(2)
Cable connector J2
JTAG header J58
Notes:
1. 0 = open, 1 = closed
2. Default switch setting

FMC Connector JTAG Bypass

When an FPGA mezzanine card (FMC) is attached to J3 or J4 it is automatically added to the
JTAG chain through electronically controlled single-pole single-throw (SPST) switches U25
and U26. The SPST switches are normally closed and transition to an open state when an
FMC is attached. Switch U25 adds an attached FMC to the JTAG chain as determined by the
FMC1_HPC_PRSNT_M2C_B signal. Switch U26 adds an attached FMC to the JTAG chain as
determined by the FMC2_LPC_PRSNT_M2C_B signal The attached FMC card must
implement a TDI-to-TDO connection using a device or bypass jumper to ensure that the
JTAG chain connects to the XC7Z020 SoC.

Clock Generation

The ZC702 board provides three clock sources for the XC7Z020 SoC.
source devices for each clock.
Table 1-11: ZC702 Board Clock Sources
Clock Name
System Clock
User Clock
PS Clock
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Switch 1
Clock
Source
SiT9102 2.5V LVDS 200
U43
Clock.
Si570 3.3V LVDS I2C programmable oscillator, 156.250
U28
Labs). See Programmable User
SIT8103 1.8V single-ended CMOS 33.3333
U65
(SiTime). See Processing System Clock
www.xilinx.com
Table 1-10.
DIP Switch SW10[1:2]
(1)
JTAG_SEL_1
0
0
1
1
Description
fixed-frequency oscillator (SiTime). See
MHz
Clock.
Source.
Feature Descriptions
(1)
Switch 2 JTAG_SEL_2
0
1
0
1
Table 1-11 lists the
System
default (Silicon
MHz
fixed frequency oscillator
MHz
Send Feedback
29