Xilinx ZCU106 User Manual page 111

Table 3-49: J4 HPC1 FMC Section C and D Connections to XCZU7EV U1
J4
Schematic Net Name
Pin
C2 FMC_HPC1_DP0_C2M_P
C3 FMC_HPC1_DP0_C2M_N
C6 FMC_HPC1_DP0_M2C_P
C7 FMC_HPC1_DP0_M2C_N
C10 FMC_HPC1_LA06_P
C11 FMC_HPC1_LA06_N
C14 FMC_HPC1_LA10_P
C15 FMC_HPC1_LA10_N
C18 FMC_HPC1_LA14_P
C19 FMC_HPC1_LA14_N
C22 NC
C23 NC
C26 NC
C27 NC
C30 FMC_HPC1_IIC_SCL
C31 FMC_HPC1_IIC_SDA
C34 GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 6 and 7.
3. FPGA U1 JTAG TCK, TMS, and TDO pins are buffered by U48 SN74AVC8T245.
4. J4 HPC1 TDO-TDI connections to U24 HPC1 FMC JTAG bypass switch (N.C. normally-closed/bypassing J4 until an FMC card
is plugged onto J4).
5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
6. U1 MGT (I/O standards do not apply).
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
I/O U1 J4
Standard Pin Pin
(7)
AJ6 D1
(7)
AJ5 D4
(6)
AK4 D5
(7)
AK3 D8
LVDS H21 D9
LVDS H22 D11
LVDS F22 D12
LVDS E22 D14
LVDS D20 D15
LVDS D21 D17
D18
D20
D21
D23
(2)
D24
(2)
D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Chapter 3: Board Component Descriptions
Schematic Net Name
VADJ_FMC_PGOOD (6)
FMC_HPC1_GBTCLK0_M2C_P
FMC_HPC1_GBTCLK0_M2C_N
FMC_HPC1_LA01_CC_P
FMC_HPC1_LA01_CC_N
FMC_HPC1_LA05_P
FMC_HPC1_LA05_N
FMC_HPC1_LA09_P
FMC_HPC1_LA09_N
FMC_HPC1_LA13_P
FMC_HPC1_LA13_N
NC
NC
NC
NC
NC
NC
FMC_HPC1_TCK_BUF
FPGA_TDO_FMC_TDI_BUF
FMC_HPC1_TDO_HPC1_TDI
UTIL_3V3_10A
FMC_HPC1_TMS_BUF
NC
GND
UTIL_3V3
UTIL_3V3
UTIL_3V3
U1
I/O Standard
Pin
(1)(7)
Y8
(1)(6)
Y7
LVDS E24
LVDS D24
LVDS G25
LVDS G26
LVDS G20
LVDS F20
LVDS C21
LVDS C22
(3)
(4)
(3)(4)
(3)
111
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